Interconnect scaling has become a major design challenge for traditional planar (2D)
integrated circuits (ICs). Three-dimensional (3D) IC that stacks multiple device layers …

Optical networks on chip (ONoC) has been proposed as a promising alternative paradigm
for electronic NoC with the benefit of optical signaling communications such as ultrahigh …

Emerging 3D integrated circuits (ICs) employ 3D network-on-chip (NoC) to improve power,
performance, and scalability. The NoC Simulator uses the microarchitecture parameters to …

With the high-performance requirement of safety-critical real-time tasks, the platforms of
many-core processors with high parallelism are widely utilized, where network-on-chip …

Current research in interfacing clusters within Hierarchical Networks-on-Chip (HNoC) as
well as interfacing NoC-based systems adopts a centralized approach. In this approach, a …

The ongoing integration of advanced functionalities in contemporary system-on-chips
(SoCs) poses significant challenges related to memory bandwidth, capacity, and thermal …

Abstract Optical Network-on-Chip (ONoC) is an emerging chip-level optical interconnection
technology to realise high-performance and power-efficient inter-core communication for …

SMART, a recently proposed dynamically reconfigurable NoC, enables single-cycle long-
distance communication by building single-bypass paths. However, such a single-cycle …

SMART NoCs achieve ultra-low latency by enabling single-cycle multiple-hop transmission
via bypass channels. However, contention along bypass channels can seriously degrade …

SMART (Single-cycle Multi-hop Asynchronous Repeated Traversal) Network-on-Chip
(NoC), a recently proposed dynamically reconfigurable NoC, enables single-cycle long …