This paper presents an innovative approach for predicting timing errors tailored to near-/sub-
threshold operations, addressing the energy-efficient requirements of digital circuits in …

Specialized architecture combined with near-and subthreshold voltage circuits emerges as
a promising candidate to improve the energy efficiency in performing complex computing …

The risk of soft errors due to radiation continues to be a significant challenge for engineers
trying to build systems that can handle harsh environments. Building systems that are …

Sharp - A Resilient Asynchronous Template Page 1 Sharp - A Resilient Asynchronous Template
Maxwell Waugaman and William Koven Reduced Energy Microsystems, San Francisco, CA …

Timing resilient designs can remove variation margins by adding error detecting logic (EDL)
that detects timing errors when execution completes within a resiliency window. Speeding …

Resilient circuits are becoming a popular alternative to cope with process, voltage, and
temperature variability under ultra-deep-submicron technology. Timing resilient …

As the VLSI design moves into ultra-deep-submicron technologies, timing margins added
due to variabilities in the manufacturing process, operation temperature and supply voltage …

As VLSI design moves into ultra-deep-submicron technologies, timing margins added to the
clock period are mandatory, to ensure correct circuit behavior under worst-case conditions …

As advancements in process technology slow and the ubiquity of mobile and embedded
devices increases, chip designers are looking to new technologies to stretch the energy …

The periodic nature of the global clock in traditional synchronous designs forces circuits to
be margined for the worst possible case of process, voltage, temperature, and data …