Energy-Efficient High-Speed dynamic logic-based One-Trit multiplier in CNTFET technology

SU Haq, E Abbasian, VK Sharma, T Khurshid… - … -International Journal of …, 2024 - Elsevier
The appeal of portable electronics, embedded systems, and other smart devices has been
steadily growing over time. The multi-valued logic (MVL) was primarily introduced to handle …

A 4.5 X noise improved split-resistance currennt mode bandgap with 18.4 ppm/° C in 28nm CMOS

R Nagulapalli, RK Palani - 2023 34th Irish Signals and Systems …, 2023 - ieeexplore.ieee.org
This paper presents a technique to limit the noise multiplication of operational amplifier used
in the bandgap core without adding any extra component. This is achieved by shifting the …

A low-power dynamic ternary full adder using carbon nanotube field-effect transistors

FM Sardroudi, M Habibi, MH Moaiyeri - AEU-International Journal of …, 2021 - Elsevier
Ternary logic uses fewer interconnects than binary logic, and smaller voltage swings are
required for the same information transfer. Carbon Nanotube transistors (CNFETs) have …

A 82μW mixed-mode sub-1V bandgap reference with 25 ppm/° C temperature co-efficient with simultaneous PTAT generation

TR Varun, R Nagulapalli, I Raja - 2021 25th International …, 2021 - ieeexplore.ieee.org
Conventional voltage mode Bandgap Reference (BGR) output is limited to 1.2 V and hence
is unsuitable for sub-1V operation in modern CMOS processes. The widely-used current …

A 9.5 nW, 0.55 V supply, CMOS current reference for low power biomedical applications

S Agarwal, A Pathy, Z Abbas - IEEE Transactions on Circuits …, 2022 - ieeexplore.ieee.org
This brief proposes an ultra-low-power current reference in TSMC 180nm technology.
Temperature compensation is achieved by taking the ratio of compensated voltage and an …

A low power miller compensation technique for two stage op-amp in 65nm CMOS technology

R Nagulapalli, K Hayatleh, S Barker… - 2019 10th …, 2019 - ieeexplore.ieee.org
A critical review of the Miller compensation technique for a two-stage operational amplifier
(op-amp) is presented in this paper. The trade-offs involved in the compensation capacitor …

A single BJT 10.2 ppm/° C bandgap reference in 45nm CMOS technology

R Nagulapalli, K Hayatleh, S Barker… - 2020 11th …, 2020 - ieeexplore.ieee.org
Bandgap reference using 2 BJT devices are well explored in the literature. Usually, less
number of BJT's would reduce the cost of the chip in modern CMOS technologies. A single …

Taguchi DoE and ANOVA: A systematic perspective for performance optimization of cross-coupled channel length modulation OTA

TB Kumar, A Panda, GK Sharma, AK Johar… - … -International Journal of …, 2020 - Elsevier
This work is a demonstration of circuit optimization using Taguchi Design of Experiments.
Cross coupled channel length modulation OTA has been considered for optimization. This …

A 0.82 V supply and 23.4 ppm/° C current mirror assisted bandgap reference

R Nagulapalli, RK Palani, K Hayatleh… - 2021 32nd Irish …, 2021 - ieeexplore.ieee.org
Traditional BGR circuits require a 1.05 V supply due to the V BE of the BJT. Deep submicron
CMOS technologies are limiting the supply voltage to less than 940mV. Hence there is a …

Broadband class-E power amplifier design using tunable output matching network

F Moloudi, H Jahanirad - AEU-International Journal of Electronics and …, 2020 - Elsevier
This paper presents a design of a broadband high-efficiency Class-E power amplifier (PA)
with a tunable output matching network (OMN). The OMN contains two main parts: The first …