Aggressive technology scaling makes modern advanced SRAMs more and more vulnerable
to soft errors such as single-node upsets (SNUs) and double-node upsets (DNUs). This …

This paper presents two novel low cost, double-and-triple-node-upset tolerant latch designs.
First, a novel low cost and double-node-upset (DNU) completely tolerant (LCDNUT) latch …

As the process feature size continues to scale down, the susceptibility of logic circuits to
radiation induced error has increased. This trend has led to the increase in sensitivity of …

The continuous advancement of CMOS technologies makes SRAMs more and more
sensitive to soft errors. This paper presents two novel radiation-hardened SRAM cell …

In deep nano-scale and high-integration CMOS technologies, storage circuits have become
increasingly sensitive to charge-sharing-induced multiple-node-upsets (MNUs) that include …

As technology size scales down toward lower two-digit nanometer dimensions, sensitivity of
CMOS circuits to radiation effects increases. Static random access memory cells (SRAMs) …

This paper presents a Schmitt trigger (ST) buffer using carbon nanotube FET (CNTFET) for
reliable low-power applications. Nanoscale circuits are more susceptible to transient faults …

With complementary metal oxide semiconductor (CMOS) technology scaling down, radiation
induced multiple-node upsets (MNUs) that include double-node-upsets and triple-node …

As Deep Neural Networks (DNNs) are increasingly deployed in safety critical and privacy
sensitive applications such as autonomous driving and biometric authentication, it is critical …

In this paper, we propose a novel high reliability and low cost DNU (Double Node Upset)
tolerant latch, HRCE (High Robust and Cost Effective) latch, for nanoscale CMOS …