A 4-to-10.5 Gb/s continuous-rate digital clock and data recovery with automatic frequency acquisition
A continuous-rate digital clock and data recovery (CDR) with automatic frequency
acquisition is presented. The proposed automatic frequency acquisition scheme …
acquisition is presented. The proposed automatic frequency acquisition scheme …
A calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolation method
A hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase
noise performance of ring oscillator based fractional-N PLLs. The proposed HPC-PI …
noise performance of ring oscillator based fractional-N PLLs. The proposed HPC-PI …
A 6.5–12.5-Gb/s half-rate single-loop all-digital referenceless CDR in 28-nm CMOS
C Yu, E Sa, S Jin, H Park, J Shin… - IEEE Journal of Solid …, 2020 - ieeexplore.ieee.org
This article presents a novel method for frequency tracking based on an extended bang-
bang phase detector (XBBPD) in a referenceless clock and data recovery (CDR) circuit. The …
bang phase detector (XBBPD) in a referenceless clock and data recovery (CDR) circuit. The …
A 2–11 GHz 7-bit high-linearity phase rotator based on wideband injection-locking multi-phase generation for high-speed serial links in 28-nm CMOS FDSOI
E Monaco, G Anzalone, G Albasini… - IEEE Journal of Solid …, 2017 - ieeexplore.ieee.org
Pushed by the ever-increasing demand of internet traffic, high-speed serial interfaces are
expected to reach 400-Gb/s aggregate data rates in near future. At receiver (RX) side, phase …
expected to reach 400-Gb/s aggregate data rates in near future. At receiver (RX) side, phase …
A 6.7–11.2 Gb/s, 2.25 pJ/bit, single-loop referenceless CDR with multi-phase, oversampling PFD in 65-nm CMOS
A single-loop referenceless clock and data recovery (CDR) with a compact frequency
acquisition scheme is presented. A bang-bang phase-frequency detector (BBPFD) is …
acquisition scheme is presented. A bang-bang phase-frequency detector (BBPFD) is …
An 8.2 Gb/s-to-10.3 Gb/s full-rate linear referenceless CDR without frequency detector in 0.18 μm CMOS
S Huang, J Cao, MM Green - IEEE Journal of Solid-State …, 2015 - ieeexplore.ieee.org
An 8.2 Gb/s-to-10.3 Gb/s full-rate referenceless CDR in 0.18 μm CMOS is presented. By
realizing an asymmetric phase detector transfer curve, the linear CDR's “single-sided” …
realizing an asymmetric phase detector transfer curve, the linear CDR's “single-sided” …
Design techniques for a 6.4–32-Gb/s 0.96-pJ/b continuous-rate CDR with stochastic frequency–phase detector
This article presents design techniques for a continuous-rate reference-free clock and data
recovery (CDR) circuit employing a stochastic frequency–phase detector (SFPD). By taking …
recovery (CDR) circuit employing a stochastic frequency–phase detector (SFPD). By taking …
A 1–16 Gb/s all-digital clock and data recovery with a wideband high-linearity phase interpolator
An all-digital phase interpolator (PI)-based clock and data recovery (CDR) is proposed in
this paper to accommodate any data rate continuously from 1 to 16 Gb/s with quadrature …
this paper to accommodate any data rate continuously from 1 to 16 Gb/s with quadrature …
The design and analysis of dual control voltages delay cell for low power and wide tuning range ring oscillators in 65 nm CMOS technology for CDR applications
In this paper three delay cell structures used in four-stage ring oscillator are evaluated. In the
first structure, the control voltage is employed to the gate of PMOS transistors which are …
first structure, the control voltage is employed to the gate of PMOS transistors which are …
A 5.2 Gb/s receiver for next-generation 8K displays in 180 nm CMOS process
T Wang, D Wei, R Ng, G Malhotra… - IEEE Journal of Solid …, 2022 - ieeexplore.ieee.org
This article presents a high-speed receiver for next-generation 8K ultra-high-definition TVs.
The receiver supports error-free communication between the timing controller and the …
The receiver supports error-free communication between the timing controller and the …