SCA evaluation and benchmarking of finalists in the NIST lightweight cryptography standardization process
Side-channel resistance is one of the primary criteria identified by NIST for use in evaluating
candidates in the Lightweight Cryptography (LWC) Standardization process. In Rounds 1 …
candidates in the Lightweight Cryptography (LWC) Standardization process. In Rounds 1 …
Constructing Committing and Leakage-Resilient Authenticated Encryption
P Struck, M Weishäupl - IACR Transactions on Symmetric Cryptology, 2024 - tosc.iacr.org
The main goal of this work is to construct authenticated encryption (AE) hat is both
committing and leakage-resilient. As a first approach for this we consider generic …
committing and leakage-resilient. As a first approach for this we consider generic …
[图书][B] Status report on the final round of the NIST lightweight cryptography standardization process
Abstract The National Institute of Standards and Technology (NIST) initiated a public
standardization process to select one or more schemes that provide Authenticated …
standardization process to select one or more schemes that provide Authenticated …
[PDF][PDF] Compress: Reducing Area and Latency of Masked Pipelined Circuits.
Masking is an effective countermeasure against side-channel attacks. It replaces every logic
gate in a computation by a gadget that performs the operation over secret sharings of the …
gate in a computation by a gadget that performs the operation over secret sharings of the …
Generalized feistel ciphers for efficient prime field masking-full version
A recent work from Eurocrypt 2023 suggests that prime-field masking has excellent potential
to improve the efficiency vs. security tradeoff of masked implementations against side …
to improve the efficiency vs. security tradeoff of masked implementations against side …
Lightweight champions of the world: Side-channel resistant open hardware for finalists in the NIST Lightweight Cryptography Standardization Process
Cryptographic competitions played a significant role in stimulating the development and
release of open hardware for cryptography. The primary reason was the focus of …
release of open hardware for cryptography. The primary reason was the focus of …
Low-Latency Masked Gadgets Robust against Physical Defaults with Application to Ascon
G Cassiers, FX Standaert… - IACR Transactions on …, 2024 - ojs.ub.ruhr-uni-bochum.de
Low-latency masked hardware implementations are known to be a difficult challenge. On the
one hand, the propagation of glitches can falsify their independence assumption (that is …
one hand, the propagation of glitches can falsify their independence assumption (that is …
Generalized Feistel Ciphers for Efficient Prime Field Masking
A recent work from Eurocrypt 2023 suggests that prime-field masking has excellent potential
to improve the efficiency vs. security tradeoff of masked implementations against side …
to improve the efficiency vs. security tradeoff of masked implementations against side …
Multiplex: TBC-Based Authenticated Encryption with Sponge-Like Rate
Authenticated Encryption (AE) modes of operation based on Tweakable Block Ciphers
(TBC) usually measure efficiency in the number of calls to the underlying primitive per …
(TBC) usually measure efficiency in the number of calls to the underlying primitive per …
Compress: Generate small and fast masked pipelined circuits
Masking is an effective countermeasure against side-channel attacks. It replaces every logic
gate in a computation by a gadget that performs the operation over secret sharings of the …
gate in a computation by a gadget that performs the operation over secret sharings of the …