An apparatus for a low energy accelerator processor architecture is disclosed. An example
arrangement is an integrated circuit that includes a system bus having a data width N, where …

(57) ABSTRACT A method for an associative memory device includes divid ing a multi-bit
mantissa A of a number X to a plurality of smaller partial mantissas Aj, offline calculating a …

Methods and apparatus for a low energy accelerator proces sor architecture with short
parallel instruction word. An integrated circuit includes a system bus having a data width N …

The present invention discloses a processor comprising three-dimensional memory (3D-M)
array (3D-processor). Instead of logic-based computation (LBC), the 3D-processor uses …

A configurable processor comprises at least an array of configurable computing elements
(CCE's). Each CCE comprises at least a three-dimensional (3-D) memory (3D-M) array; an …

In described examples, a time-domain analyzer is arranged to generate an indication of a
number of high-frequency events of an electrical monitor signal that includes a fundamental …

A configurable processor comprises a memory die and a logic die. The memory die
comprises a programmable memory array for storing a look-up table (LUT) for a …

An apparatus for a low energy accelerator processor archi tecture is disclosed. An example
arrangement is an inte grated circuit that includes a system bus having a data width N …

The present invention discloses a first preferred processor comprising a fixed look-up table
circuit (LTC) and a writable LTC. The fixed LTC realizes at least a common function while the …

In described examples, a time-domain analyzer is arranged to generate an indication of a
number of high-frequency events of an electrical monitor signal that includes a funda mental …