The test design cost of a circuit capable of accessing an external memory is reduced. There
is included a built-in self-test circuit for use in testing an external memory sepa rately from a …

A method and system conduct built-in-self-test (BIST) in a circuit under test. After allocating
at least one memory segment with a predetermined size in at least one memory module as a …

(57) ABSTRACT A method for Verifying the accuracy of memory testing soft ware is
disclosed. A built-in self test (BIST) fail control function is utilized to generate multiple …

A fault diagnosis method for a semiconductor device in which a memory and a register are
monolithically integrated is pro vided. The fault diagnosis method is composed of first test …

E. Stuckman (57) ABSTRACT An integrated circuit is interfaced with at least one dynamic
random access memory (DRAM) via a memory interface. A plurality of user test options are …

US20120137185A1 - Method and apparatus for performing a memory built-in self-test on a
plurality of memory element arrays - Google Patents US20120137185A1 - Method and …

In an embodiment, a model may be created using a register transfer level (RTL)
representation of the controller and the circuitry in the communication fabric to the controller …

A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP
domain (106) of a device using a reduced pin count, high speed DDR interface (202). The …

A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP
domain (106) of a device using a reduced pin count, high speed DDR interface (202). The …

This invention uniquely partitions the pBIST ROM for storing program and data information.
The pBIST unit selectively loads both the algorithm and data, the algorithm only or the data …