A 0.15-to-0.5 V body-driven dynamic comparator with rail-to-rail ICMR
In this paper, a novel dynamic body-driven ultra-low voltage (ULV) comparator is presented.
The proposed topology takes advantage of the back-gate configuration by driving the input …
The proposed topology takes advantage of the back-gate configuration by driving the input …
Analysis and background self-calibration of comparator offset in loop-unrolled SAR ADCs
In conventional charge redistribution successive approximation register (SAR) ADCs that
use a single comparator, the comparator offset causes no distortion but a dc shift in the …
use a single comparator, the comparator offset causes no distortion but a dc shift in the …
A sar adc with a moscap-dac
T Rabuske, J Fernandes - IEEE Journal of Solid-State Circuits, 2016 - ieeexplore.ieee.org
The linearity of the vast majority of the ADC topologies is limited by the linearity of the circuit
elements employed in their design, such as resistors and capacitors. This paper presents a …
elements employed in their design, such as resistors and capacitors. This paper presents a …
A 0.4-V 10-bit 10-KS/s SAR ADC in 0.18 μm CMOS for low energy wireless senor network chip
X Xin, JP Cai, TT Chen, Q Di Yang - Microelectronics Journal, 2019 - Elsevier
Abstract A 10-bit 10-KS/s asynchronous successive approximation register (SAR) analogue-
to-digital converter (ADC) in 180 nm CMOS process is proposed for low energy wireless …
to-digital converter (ADC) in 180 nm CMOS process is proposed for low energy wireless …
A 0.3 V 8-bit 8.9 fJ/con.-step SAR ADC with sub-DAC merged switching for bio-sensors
W Guo, Z Zhu - Microelectronics journal, 2017 - Elsevier
Abstract An 8-bit 10 kS/s 0.3 V ultra-low power successive approximation register (SAR)
analog-to-digital converter (ADC) is proposed. On account of the presented sub-DAC …
analog-to-digital converter (ADC) is proposed. On account of the presented sub-DAC …
Design of a dynamic ADC comparator with low power and low delay time for IoT application
In this paper, a low power and low delay comparator circuit for the IoT applications has been
designed and analyzed. In the proposed comparator, two different voltage levels have been …
designed and analyzed. In the proposed comparator, two different voltage levels have been …
A high-speed, low-offset and low-power differential comparator for analog to digital converters
M Nasrollahpour, CH Yen… - 2017 International SoC …, 2017 - ieeexplore.ieee.org
Analysis and design of a high-speed comparator with improved input referred offset is
presented in this paper. The proposed comparator is designed in TSMC low power CMOS …
presented in this paper. The proposed comparator is designed in TSMC low power CMOS …
A 0.6-V 9-bit 1-MS/s charging sharing SAR ADC with judging-window switching logic and independent reset comparator for power-effective applications
This brief presents a 9-bit energy-effective charge sharing (CS) SAR ADC by using judging
window switching logic. The power consumption of the DAC is greatly reduced when the …
window switching logic. The power consumption of the DAC is greatly reduced when the …
A nanowatt noise-shaping SAR ADC for passive wireless sensor node application
P Yang, Z Zhang - IEICE Electronics Express, 2022 - jstage.jst.go.jp
This paper presents a novel first-order noise-shaping successive approximation register
(SAR) analog-to-digital converter (ADC) for passive wireless sensor node application. To …
(SAR) analog-to-digital converter (ADC) for passive wireless sensor node application. To …
Noise-aware simulation-based sizing and optimization of clocked comparators
T Rabuske, J Fernandes - Analog Integrated Circuits and Signal …, 2014 - Springer
Comparators are essential components of ADCs, and largely affect their overall
performance. Among the performance metrics of the comparator, the noise is the most …
performance. Among the performance metrics of the comparator, the noise is the most …