Techniques are provided for pre-charging NAND strings during a programming operation.
The NAND strings are in a block that is divided into vertical sub-blocks. During a pre-charge …

(57) ABSTRACT A vertical NAND string in a channel-stacked 3D memory device may be
programmed using ISPP scheme, wherein a preparation step is introduced immediately after …

(57) ABSTRACT A semiconductor device includes a memory string coupled between a
source line and a bit line and including a plurality of memory cells, a plurality of word lines, a …

US11587619B2 - Block configuration for memory device with separate sub-blocks - Google
Patents US11587619B2 - Block configuration for memory device with separate sub-blocks …

G11C11/56—Digital stores characterised by the use of particular electric or magnetic
storage elements; Storage elements therefor using storage elements with more than two …

Apparatuses and techniques are described for optimizing programming in a memory device
in which memory cells can be programmed using single bit per cell programming and …

A 3D memory device may include a first set of memory layers, a second set of memory layers
above the first set of memory layers, and a first dummy memory layer between the first and …

The memory device includes a block with a plurality of memory cells arranged in a plurality
of data word lines, which are arranged in sub-blocks that are not separated from one …

Technology is disclosed herein reconfiguring word lines as either data word lines or dummy
word lines. In a sub-block mode reconfigurable word lines are used as dummy word lines …

Memory cells are arranged as NAND strings to form a block divided into sub-blocks, and
each NAND string includes a dummy memory cell connected to a dummy word line. Memory …