The present disclosure relates to a memory device and a memory system including the
same. The memory device includes a memory cell storing data, a voltage generation circuit …

(57) ABSTRACT A circuit includes a program controller configured to per form a program
operation with interleaved program-verify loops to program memory cells in a same block …

A semiconductor memory device includes: a memory cell array including a plurality of NAND
strings, each of the plurality of NAND strings including a plurality of memory cell transistors …

In a method for reading a memory device including a first memory cell string, in a pre-verify
stage, a first verify voltage is applied on a gate terminal of a selected memory cell of the first …

A memory apparatus and method of operation are provided. The apparatus includes
memory cells connected to word lines and disposed in strings. A control means is coupled to …

An apparatus is provided that includes a memory die having a first memory cell, and a
controller connected to the memory die. The controller is configured to apply a plurality of …

Apparatuses and techniques are described for detecting a defect in a memory cell array
during program operations. A defect can be detected by comparing the programming speed …

An apparatus that includes a word line with a plurality of memory cells that are able to be
programmed to a plurality of data states is provided. The apparatus further includes a …

G11C11/56—Digital stores characterised by the use of particular electric or magnetic
storage elements; Storage elements therefor using storage elements with more than two …

A method for memory block management includes identifying a first group of bit lines
corresponding to memory blocks of a 3-dimensional memory array. The method also …