Memory device, memory system including the memory device
JH Lee, JH Kim, KH Baek, JH Lee - US Patent 10,818,360, 2020 - Google Patents
The present disclosure relates to a memory device and a memory system including the
same. The memory device includes a memory cell storing data, a voltage generation circuit …
same. The memory device includes a memory cell storing data, a voltage generation circuit …
Interleaved program and verify in non-volatile memory
X Yang, HY Tseng, D Dutta - US Patent 10,885,994, 2021 - Google Patents
(57) ABSTRACT A circuit includes a program controller configured to per form a program
operation with interleaved program-verify loops to program memory cells in a same block …
operation with interleaved program-verify loops to program memory cells in a same block …
Semiconductor flash memory device with voltage control on completion of a program operation and subsequent to completion of the program operation
K Kikuchi, Y Shimura - US Patent 11,948,642, 2024 - Google Patents
A semiconductor memory device includes: a memory cell array including a plurality of NAND
strings, each of the plurality of NAND strings including a plurality of memory cell transistors …
strings, each of the plurality of NAND strings including a plurality of memory cell transistors …
Architecture and method for NAND memory operation
LEE Changhyun, XN Zhao, H Li - US Patent 11,901,023, 2024 - Google Patents
In a method for reading a memory device including a first memory cell string, in a pre-verify
stage, a first verify voltage is applied on a gate terminal of a selected memory cell of the first …
stage, a first verify voltage is applied on a gate terminal of a selected memory cell of the first …
Two-side staircase pre-charge in sub-block mode of three-tier non-volatile memory architecture
A memory apparatus and method of operation are provided. The apparatus includes
memory cells connected to word lines and disposed in strings. A control means is coupled to …
memory cells connected to word lines and disposed in strings. A control means is coupled to …
Apparatus and methods for programming memory cells
M Wang, L Li, K Zhang - US Patent 11,908,524, 2024 - Google Patents
An apparatus is provided that includes a memory die having a first memory cell, and a
controller connected to the memory die. The controller is configured to apply a plurality of …
controller connected to the memory die. The controller is configured to apply a plurality of …
State-by-state program loop delta detection mode for detecting a defective memory array
L Li, C Xu, Q Zhen - US Patent 11,775,374, 2023 - Google Patents
Apparatuses and techniques are described for detecting a defect in a memory cell array
during program operations. A defect can be detected by comparing the programming speed …
during program operations. A defect can be detected by comparing the programming speed …
Programming techniques with fewer verify pulses to improve performance
A Prakash, A Khandelwal - US Patent 11,410,739, 2022 - Google Patents
An apparatus that includes a word line with a plurality of memory cells that are able to be
programmed to a plurality of data states is provided. The apparatus further includes a …
programmed to a plurality of data states is provided. The apparatus further includes a …
Sequential write and sequential write verify in memory device
K Sakui - US Patent 11,631,460, 2023 - Google Patents
G11C11/56—Digital stores characterised by the use of particular electric or magnetic
storage elements; Storage elements therefor using storage elements with more than two …
storage elements; Storage elements therefor using storage elements with more than two …
Systems and methods for defining memory sub-blocks
M Nishikawa, H Chibvongodze - US Patent 11,487,454, 2022 - Google Patents
A method for memory block management includes identifying a first group of bit lines
corresponding to memory blocks of a 3-dimensional memory array. The method also …
corresponding to memory blocks of a 3-dimensional memory array. The method also …