Transistor network optimization represents an effective way of improving VLSI circuits. This
paper proposes a novel method to automatically generate networks with minimal transistor …

Transistor network minimization is an important step in designing new standard cells.
Existing methods for minimizing transistor networks all rely on some heuristic techniques …

This paper presents a systematic way to derive digital circuits from Binary Decision
Diagrams (BDDs). It is well known that BDD nodes correspond to the Shannon …

This paper presents an evaluation of the data structures that implement the unique tables
used to represent the Binary Decision Diagrams (BDD) nodes in the strong canonical form of …

This paper presents an improvement in our previous methodology to generate efficient
transistor networks. The proposed method applies graph-based optimizations and is …

The transistor arrangement optimization is an effective possibility to improve logic gates and,
consequently, VLSI design. This paper presents a graph-based methodology to determine if …

Nowadays, design issues related to physical design and scalability are becoming the main
bottlenecks of modern tools for technology mapping, limiting the usage of large cells. On the …

This paper presents a new methodology to generate efficient transistor networks. Transistor-
level optimization consists in an effective possibility to increase design quality when …

The transistor arrangement optimization is an effective possibility to improve VLSI design,
especially when generating CMOS logic gates to be inserted in standard cell libraries. This …

The number of transistors required for implementing a logic function is an essential
consideration in digital VLSI design. While the generation of a series-parallel network can …