SOI-LDMOS Transistors With Optimized Partial n+ Buried Layer for Improved Performance in Power Amplifier Applications
KNS Nikhil, N DasGupta, A DasGupta… - … on Electron Devices, 2018 - ieeexplore.ieee.org
In this paper, for the first time, we demonstrate the improvement in power capability and safe
operating area of silicon-on-insulator laterally double-diffused MOS (SOI-LDMOS) …
operating area of silicon-on-insulator laterally double-diffused MOS (SOI-LDMOS) …
Design of drain-extended MOS devices using RESURF techniques for high switching performance and avalanche reliability
The drift region of conventional drain extended NMOS (DeNMOS_C) is engineered to
reduce gate charge for high performance and to enhance avalanche ruggedness for …
reduce gate charge for high performance and to enhance avalanche ruggedness for …
Analysis and modeling of the snapback voltage for varying buried oxide thickness in SOI-LDMOS transistors
KNS Nikhil, N DasGupta, A DasGupta… - … on Electron Devices, 2016 - ieeexplore.ieee.org
In this paper, for the first time, we report a nonmonotonic dependence of the snapback
voltage (V sb) on the buried oxide thickness (tBOX) in silicon-on-insulator laterally double …
voltage (V sb) on the buried oxide thickness (tBOX) in silicon-on-insulator laterally double …
Analysis and optimization of lateral thin-film silicon-on-insulator (SOI) MOSFET transistors
I Cortés, G Toulon, F Morancho… - Microelectronics …, 2012 - Elsevier
This paper is focused on the analysis and optimization of power N-type LDMOS (LDNMOS)
transistors (VBR> 120V) with the purpose of being integrated in a new generation of Smart …
transistors (VBR> 120V) with the purpose of being integrated in a new generation of Smart …
Design and optimization of high voltage LDMOS transistors on 0.18 μm SOI CMOS technology
G Toulon, I Cortes, F Morancho… - Solid-state …, 2011 - Elsevier
This paper analyses the voltage capability of lateral power (V BR> 120 V) P-and N-channel
MOS transistors manufactured on a 0.18 μm SOI CMOS technology by means of TCAD …
MOS transistors manufactured on a 0.18 μm SOI CMOS technology by means of TCAD …
Applicability of Channel Doping Gradient in the Design of a Short Channel (0.1 µm) LDMOS Transistor for Integrated Power and RF Applications
S Fayaz, N Hakim, GM Rather - Transactions on Electrical and Electronic …, 2024 - Springer
In this work, we have proposed a channel engineering technique for the performance
enhancement of a short channel Laterally Diffused Metal–Oxide–Semiconductor (LDMOS) …
enhancement of a short channel Laterally Diffused Metal–Oxide–Semiconductor (LDMOS) …
The effect of dual dummy gate in the drift region on the on-state performance of SOI-LDMOS transistor for power amplifier application
J Sahoo, R Mahapatra - Silicon, 2022 - Springer
The present work proposes a novel dual dummy gate Silicon-on-Insulator Laterally Double
Diffused Metal-Oxide-Semiconductor (SOI-LDMOS) transistor. TCAD simulation shows …
Diffused Metal-Oxide-Semiconductor (SOI-LDMOS) transistor. TCAD simulation shows …
A super junction SiGe low-loss fast switching power diode
M Li, G Yong - Chinese Physics B, 2009 - iopscience.iop.org
This paper proposes a novel super junction (SJ) SiGe switching power diode which has a
columnar structure of alternating p− and n− doped pillar substituting conventional n− base …
columnar structure of alternating p− and n− doped pillar substituting conventional n− base …
Analysis and Optimization of LUDMOS Transistors on a 0.18 um SOI CMOS Technology
G Toulon, I Cortés, F Morancho, B Villard - International Journal of …, 2010 - infona.pl
This paper is focused on the design and optimization of power LDMOS transistors (V br>
120 Volts) with the purpose of being integrated in a new generation of Smart Power …
120 Volts) with the purpose of being integrated in a new generation of Smart Power …
Analysis and optimisation of lateral thin-film silicon-on-insulator (SOI) PMOS transistor with an NBL layer in the drift region
I Cortés, G Toulon, F Morancho, D Flores… - Solid-state …, 2012 - Elsevier
This paper analyses the experimental results of voltage capability (VBR> 120V) and output
characteristics of a new lateral power P-channel MOS transistors manufactured on a 0.18 …
characteristics of a new lateral power P-channel MOS transistors manufactured on a 0.18 …