[图书][B] Why systolic architecture?
HT Kung - 1982 - eecs.harvard.edu
Roughly, the cycle for developing a special-purpose system can be divided into three
phases–task definition, design, and implementation. During task definition, some system …
phases–task definition, design, and implementation. During task definition, some system …
Retiming synchronous circuitry
CE Leiserson, JB Saxe - Algorithmica, 1991 - Springer
This paper describes a circuit transformation called retiming in which registers are added at
some points in a circuit and removed from others in such a way that the functional behavior …
some points in a circuit and removed from others in such a way that the functional behavior …
Constrained parametric min-cuts for automatic object segmentation
J Carreira, C Sminchisescu - 2010 IEEE Computer Society …, 2010 - ieeexplore.ieee.org
We present a novel framework for generating and ranking plausible objects hypotheses in
an image using bottom-up processes and mid-level cues. The object hypotheses are …
an image using bottom-up processes and mid-level cues. The object hypotheses are …
[图书][B] Models of computation
JE Savage - 1998 - dna.caltech.edu
Models of Computation.ppt [Read-Only] Page 1 Models of Computation John E Savage
Computer Science Brown University CBSSS 2004 July 16, 2004 Page 2 CBSSS: JE Savage …
Computer Science Brown University CBSSS 2004 July 16, 2004 Page 2 CBSSS: JE Savage …
[PDF][PDF] Darkroom: compiling high-level image processing code into hardware pipelines.
Specialized image signal processors (ISPs) exploit the structure of image processing
pipelines to minimize memory bandwidth using the architectural pattern of line-buffering …
pipelines to minimize memory bandwidth using the architectural pattern of line-buffering …
[图书][B] Parallel computation: models and methods
SG Akl - 1997 - dl.acm.org
Parallel computation | Guide books skip to main content ACM Digital Library home ACM home
Google, Inc. (search) Advanced Search Browse About Sign in Register Advanced Search …
Google, Inc. (search) Advanced Search Browse About Sign in Register Advanced Search …
RaPiD—Reconfigurable pipelined datapath
C Ebeling, DC Cronquist, P Franklin - Field-Programmable Logic Smart …, 1996 - Springer
Configurable computing has captured the imagination of many architects who want the
performance of application-specific hardware combined with the reprogrammability of …
performance of application-specific hardware combined with the reprogrammability of …
Optimizing synchronous circuitry by retiming (preliminary version)
CE Leiserson, FM Rose, JB Saxe - Third Caltech conference on very large …, 1983 - Springer
This paper explores circuit optimization within a graph-theoretic framework. The vertices of
the graph are combinational logic elements with assigned numerical propagation delays …
the graph are combinational logic elements with assigned numerical propagation delays …
Optimizing synchronous systems
CE Leiserson, JB Saxe - 22nd Annual Symposium on …, 1981 - ieeexplore.ieee.org
The complexity of integrated-circuit chips produced today makes it feasible to build
inexpensive, special-purpose subsystems that rapidly solve sophisticated problems on …
inexpensive, special-purpose subsystems that rapidly solve sophisticated problems on …
Regular iterative algorithms and their implementation on processor arrays
SK Rao, T Kailath - Proceedings of the IEEE, 1988 - ieeexplore.ieee.org
Some recent results are summarized concerning a class of algorithms known as regular
iterative algorithms, particularly with respect to their implementations on processor arrays …
iterative algorithms, particularly with respect to their implementations on processor arrays …