Design of high speed and low power 4-bit comparator using FGMOS

R Gupta, R Gupta, S Sharma - AEU-International Journal of Electronics and …, 2017 - Elsevier
This paper presents a novel low power and high speed 4-bit comparator extendable to 64-
bits using floating-gate MOSFET (FGMOS). Here, we have exploited the unique feature of …

Design of CMOS full subtractor using 10T for object detection application

MM Basha, KV Ramanaiah… - International Journal of …, 2018 - inderscienceonline.com
This paper presents the design of full subtractor (FS), which is able to operate at low voltage
and low power. In this method, 2 XOR gates with 1 MUX circuit are used to design the 10T …

A high-speed, low-power, and area-efficient FGMOS-based full adder

R Gupta, R Gupta, S Sharma - IETE Journal of Research, 2022 - Taylor & Francis
Full adder is one of the fundamental components of very large-scale digital integrated
systems, capable of performing all arithmetic operations. High-performance full adders are …

Bulk-driven inverter configuration and its application for implementing ring oscillator

M Javed, R Gupta, S Sharma - 2023 IEEE International …, 2023 - ieeexplore.ieee.org
A digital inverter based on CMOS design is implemented using the bulk-driven (BD)
technique for both floating gate (FG) and quasi floating gate (QFG) MOS. It has all the …

Application of quasi floating-gate MOS transistor in the design of ring oscillator

R Gupta, R Gupta, S Sharma - 2016 3rd International …, 2016 - ieeexplore.ieee.org
This paper presents the design of high performance ring oscillator using quasi floating-gate
MOSFET (QFGMOS) which is suitable for low voltage and low power design in the modern …

Design and Comparative analysis of Mux Tree using Different Low Power Design Techniques

K Sharma, A Kumar - 2021 6th International Conference on …, 2021 - ieeexplore.ieee.org
The work present in this paper depicts the design and thorough comparative analysis of a
digital circuit namely, 4X1 mux tree (data selector) using different Low Power design …

Log Domain Integrator using Quasi-Floating Gate MOSFET

H Kaur, R Gupta, S Sharma - Recent Advances in Electrical & …, 2018 - ingentaconnect.com
Background: A MOS transistor operating in weak inversion exhibits logarithmic behavior and
could serve as replacement of bipolar transistors which have often been employed in …

Design and Simulation of CMOS Circuit Structure for CTL-CTM Crosstalk Cancellation Method in High-Speed Interconnects

H Sun, Y Wang, Y Zhao, X Li - Progress In Electromagnetics Research …, 2021 - jpier.org
A circuit module for coupled transmission line channel transmission matrix (CTL-CTM)
crosstalk cancellation is designed and simulated by using CMOS technology in a high …

[PDF][PDF] Design and Performance Analysis of 4-input Multiplexer Tree using FGMOS

K Sharma, V Niranjan, A Kumar, SC Lalu - AIJR Proceedings, 2021 - researchgate.net
The work proposed in this paper presents the design of Ultra Lowpower–Lowvoltage2-input
multiplexer using Floating Gate MOS (FGMOS), which is subsequently used to design and …

Performance enhancement of digital gates using threshold logic

R Gupta, R Gupta, S Sharma - 2016 3rd International …, 2016 - ieeexplore.ieee.org
This paper explores the use of threshold logic for the design of digital circuits well suited for
low voltage and low power applications. CMOS digital gates such as AND, OR, NAND, NOR …