A configurable floating-point multiple-precision processing element for HPC and AI converged computing

W Mao, K Li, Q Cheng, L Dai, B Li, X Xie… - … Transactions on Very …, 2021 - ieeexplore.ieee.org
There is an emerging need to design configurable accelerators for the high-performance
computing (HPC) and artificial intelligence (AI) applications in different precisions. Thus, the …

Design of low power and high speed Carry Select Adder using Brent Kung adder

P Saxena - 2015 international conference on VLSI systems …, 2015 - ieeexplore.ieee.org
In this paper, Carry Select Adder (CSA) architectures are proposed using parallel prefix
adders. Instead of using dual Ripple Carry Adders (RCA), parallel prefix adder ie, Brent …

[PDF][PDF] Design and performance analysis of various adders using verilog

DPS Maroju SaiKumar - … journal of computer science and mobile …, 2013 - academia.edu
Adders are one of the most widely digital components in the digital integrated circuit design
and are the necessary part of Digital Signal Processing (DSP) applications. With the …

Design and implementation of high speed modified booth multiplier using hybrid adder

D Govekar, A Amonkar - 2017 International Conference on …, 2017 - ieeexplore.ieee.org
Multiplier is one of the most desirable component in most of the processors designed today.
The speed of multiplier determines the speed of the processor. So there is a need of high …

[PDF][PDF] Analysis of low power, area-efficient and high speed fast adder

P Saxena, U Purohit, P Joshi - … Journal of Advanced Research in Computer …, 2013 - Citeseer
In electronics, adder is a digital circuit that performs addition of numbers. To perform fast
arithmetic operations, carry select adder (CSLA) is one of the fastest adders used in many …

Implementation of FIR filter using reversible modified carry select adder

R Arun Sekar, S Sasipriya - Concurrency and Computation …, 2019 - Wiley Online Library
Any arithmetic operation can be performed using the method of Reversible process which
allows minimum arithmetic execution. An essential scenario for achieving this condition is …

Optimized structures of hybrid ripple carry and hierarchical carry lookahead adders

A Ibrahim, F Gebali - Microelectronics Journal, 2015 - Elsevier
This paper proposes improved structures for fast adders that include carry lookahead (CLA)
and hierarchical carry lookahead (HCLA). Also, it proposes optimized novel structures of …

Implementation of high speed and low power carry select adder with BEC

NA Gudala, T Ytterdal, JJ Lee… - 2021 IEEE International …, 2021 - ieeexplore.ieee.org
One of the most substantial areas of research in VLSI is the design of power-efficient and
high-speed data path logic systems. The speed of addition is constrained in digital adders …

16 bit power efficient carry select adder

N Gaur, A Mehra, P Kumar… - 2019 6th International …, 2019 - ieeexplore.ieee.org
The paper presents a new and modified area and power efficient carry select adder is
proposed using Weinberger architecture and it is compared for efficiency with modified …

Design and implementation of high speed hybrid carry select adder

A Simson, S Deepak - 2021 International conference on …, 2021 - ieeexplore.ieee.org
Adder is considered the principle unit of every arithmetic and logical operation. Carry select
adder (CSLA) is an adder that helps to speed up operations of several arithmetic function …