As the trends of process scaling make memory systems an even more crucial bottleneck, the
importance of latency hiding techniques such as prefetching grows further. However, naively …

Contemporary DRAM systems have maintained impressive scaling by managing a careful
balance between performance, power, and storage density. In achieving these goals, a …

In emerging and future high-end processor systems, tolerating increasing cache miss
latency and properly managing memory bandwidth will be critical to achieving high …

Hardware data prefetching is widely adopted to hide long memory latency. A hardware data
prefetcher predicts the memory address that will be accessed in the near future and fetches …

Chip multiprocessor (CMP) systems have become inevitable to meet high computing
demands. In such systems sharing of resources is imperative for better resource utilisation …

This paper presents Limoncello, a novel software system that dynamically configures data
prefetchers for high-utilization systems. We demonstrate that in resource-constrained …

This paper presents a low complexity table-based approach to delta correlation prefetching.
Our approach uses a table indexed by the load address which stores the latest deltas …

A semiconductor device includes a plurality of memory controllers each of which includes a
local buffer, a global buffer coupled to the plurality of memory controllers and including …

In multi-core systems, an application's prefetcher can interfere with the memory requests of
other applications using the shared resources, such as last level cache and memory …

A memory system comprises memory devices coupled to a memory controller via a memory
interface bus, the memory controller for receiving one or more memory requests via an …