Modern processors are using increasingly larger sized on-chip caches. Also, with each
CMOS technology generation, there has been a significant increase in their leakage energy …

Constantly advancing integration capability is paving the way for the construction of the
extremely large scale continuum of the Internet where entities or things from vastly varied …

The disparity between memory and CPU have been ameliorated by the introduction of
Network-on-Chip-based Chip-Multiprocessors (NoC-based CMPS). However, power …

Bias temperature instability (BTI) and soft errors are major reliability concerns for deep
submicron technologies. Negative BTI leads to an increase of the threshold voltage of PMOS …

Fault-Tolerant Voltage-Scalable (FTVS) SRAM cache architectures are a promising
approach to improve energy efficiency of memories in the presence of nanoscale process …

The last level on-chip cache (LLC) is becoming bigger and more complex to effectively
support the various localities coming from multiple cores and threads running concurrently in …

We propose a novel dynamic voltage scaling (DVS) approach for reliable and energy
efficient cache memories. First, we demonstrate that, as memories age, leakage power …

In this paper, we show how beneficial effects of aging on static power consumption can be
exploited to design reliable drowsy cache memories adopting dynamic voltage scaling …

Improvements in semiconductor nanotechnology made chip multiprocessors the reference
architecture for high-performance microprocessors. CMPs usually adopt large Last-Level …

Power management for large last-level caches (LLCs) is important in chip multiprocessors
(CMPs), as the leakage power of LLCs accounts for a significant fraction of the limited on …