Replacing testing with formal verification in intel coretm i7 processor execution engine validation

R Kaivola, R Ghughal, N Narasimhan, A Telfer… - … on Computer Aided …, 2009 - Springer
Formal verification of arithmetic datapaths has been part of the established methodology for
most Intel processor designs over the last years, usually in the role of supplementing more …

End-to-end verification of processors with ISA-Formal

A Reid, R Chen, A Deligiannis, D Gilday… - … Aided Verification: 28th …, 2016 - Springer
Despite 20+ years of research on processor verification, it remains hard to use formal
verification techniques in commercial processor development. There are two significant …

Code-level model checking in the software development workflow

N Chong, B Cook, K Kallas, K Khazem… - Proceedings of the …, 2020 - dl.acm.org
This experience report describes a style of applying symbolic model checking developed
over the course of four years at Amazon Web Services (AWS). Lessons learned are drawn …

Finding bugs in an alpha microprocessor using satisfiability solvers

P Bjesse, T Leonard, A Mokkedem - … , CAV 2001 Paris, France, July 18–22 …, 2001 - Springer
We describe the techniques we have used to search for bugs in the memory subsystem of a
next-generation Alpha microprocessor. Our approach is based on two model checking …

An industrially effective environment for formal hardware verification

CJH Seger, RB Jones, JW O'Leary… - … on Computer-Aided …, 2005 - ieeexplore.ieee.org
The Forte formal verification environment for datapath-dominated hardware is described.
Forte has proven to be effective in large-scale industrial trials and combines an efficient …

Code‐level model checking in the software development workflow at Amazon web services

N Chong, B Cook, J Eidelman, K Kallas… - Software: Practice …, 2021 - Wiley Online Library
This article describes a style of applying symbolic model checking developed over the
course of four years at Amazon Web Services (AWS). Lessons learned are drawn from …

RTLCheck: Verifying the memory consistency of RTL designs

YA Manerkar, D Lustig, M Martonosi… - Proceedings of the 50th …, 2017 - dl.acm.org
Paramount to the viability of a parallel architecture is the correct implementation of its
memory consistency model (MCM). Although tools exist for verifying consistency models at …

Fermionic field theory for trees and forests

S Caracciolo, JL Jacobsen, H Saleur, AD Sokal… - Physical review …, 2004 - APS
We prove a generalization of Kirchhoff's matrix-tree theorem in which a large class of
combinatorial objects are represented by non-Gaussian Grassmann integrals. As a special …

A short historical survey of functional hardware languages

G Chen - International Scholarly Research Notices, 2012 - Wiley Online Library
Functional programming languages offer a high degree of abstractions and clean semantics,
which are desirable for hardware descriptions. This short historical survey is about functional …

A flexible formal verification framework for industrial scale validation

A Slobodová, J Davis, S Swords… - Ninth ACM/IEEE …, 2011 - ieeexplore.ieee.org
In recent years, leading microprocessor companies have made huge investments to improve
the reliability of their products. Besides expanding their validation and CAD tools teams, they …