State of the art and future perspectives in advanced CMOS technology

HH Radamson, H Zhu, Z Wu, X He, H Lin, J Liu… - Nanomaterials, 2020 - mdpi.com
The international technology roadmap of semiconductors (ITRS) is approaching the
historical end point and we observe that the semiconductor industry is driving …

Toward attojoule switching energy in logic transistors

S Datta, W Chakraborty, M Radosavljevic - Science, 2022 - science.org
Advances in the theory of semiconductors in the 1930s in addition to the purification of
germanium and silicon crystals in the 1940s enabled the point-contact junction transistor in …

A review of the gate-all-around nanosheet FET process opportunities

S Mukesh, J Zhang - Electronics, 2022 - mdpi.com
In this paper, the innovations in device design of the gate-all-around (GAA) nanosheet FET
are reviewed. These innovations span enablement of multiple threshold voltages and …

Design optimization of three-stacked nanosheet FET from self-heating effects perspective

S Rathore, RK Jaisawal, PN Kondekar… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
Self-heating effect (SHE) is a severe issue arising in the nanoscale field-effect transistors
(FETs). It raises the device's lattice temperature several degrees higher than the ambient …

New structure transistors for advanced technology node CMOS ICs

Q Zhang, Y Zhang, Y Luo, H Yin - National Science Review, 2024 - academic.oup.com
Over recent decades, advancements in complementary metal-oxide-semiconductor
integrated circuits (ICs) have mainly relied on structural innovations in transistors. From …

Demonstration of a nanosheet FET with high thermal conductivity material as buried oxide: Mitigation of self-heating effect

S Rathore, RK Jaisawal, PN Kondekar… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Self-heating-induced thermal degradation is a severe issue in nonplanar MOS architectures.
Especially in stacked gate-all-around (GAA) nanosheet FET (NSFET), the self-heating effect …

Optimization of structure and electrical characteristics for four-layer vertically-stacked horizontal gate-all-around Si nanosheets devices

Q Zhang, J Gu, R Xu, L Cao, J Li, Z Wu, G Wang, J Yao… - Nanomaterials, 2021 - mdpi.com
In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si
nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release …

Analysis of self-heating effects in multi-nanosheet FET considering bottom isolation and package options

C Yoo, J Chang, Y Seon, H Kim… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
Self-heating effects (SHEs) of multi-nanosheet FET (mNS-FET) at the 3-nm technology node
were analyzed at the device and circuit level considering the introduction of punchthrough …

A critical review on performance, reliability, and fabrication challenges in nanosheet FET for future analog/digital IC applications

S Valasa, S Tayal, LR Thoutam, J Ajayan… - Micro and …, 2022 - Elsevier
This article critically reviews the fabrication challenges, emerging materials (wafer, high-k
oxide, gate metal, channel materials), dimensional influences, thermal effects, growth …

Review of nanosheet metrology opportunities for technology readiness

MA Breton, D Schmidt, A Greene… - Journal of Micro …, 2022 - spiedigitallibrary.org
Over the past several years, stacked nanosheet gate-all-around (GAA) transistors captured
the focus of the semiconductor industry and have been identified as the lead architecture to …