We study how nitridation, applied to SiON gate layers, impacts the reliability of planar metal-
oxide-semiconductor field effect transistors (MOSFETs) subjected to negative and positive …

Forksheet (FS) FETs are a novel transistor architecture consisting of vertically stacked nFET
and pFET sheets at opposite sides of a dielectric wall. The wall allows reducing the p-to …

This work reports an on-chip heater structure fabricated in the Front End of Line (FEOL) on a
versatile ring-oscillator (RO) array utilized to conduct statistical characterization of on-chip …

We report TCAD simulation studies on nanowire (NW), nanosheet (NS) and forksheet (FS)
FET hot-carrier relia-bility. The simulations entail i) solving the Boltzmann transport equation …

We simulate the spatial profile of trapped charge in the forksheet FET wall under hot-carrier
stress by calculating carrier distribution functions and using a non-radiative multiphonon …

Charge trapping at oxide defects poses a serious reliability concern in MOS transistors. For
scaled technology nodes, the impact of charge-trapping events on device behavior becomes …

Charge trapping at oxide defects is a serious reliability concern in MOS transistors. For
scaled technology nodes, the impact of charge-trapping events on the device behavior …

A yield prediction model with a corresponding cost of the ownership (CoO) and turn-around-
time (TAT) analysis is studied on imec's advanced technology nodes that include EUV and …

This article presents an evaluation of the CMOS logic performance of a junctionless (JL)
forksheet based on 3-D numerical simulation. The study investigates the transfer …

The forksheet (FSH) device architecture is a possible candidate towards continued logic cell
downscaling. It consists of vertically stacked n-and p-type sheets at opposing sides of a …