Described is a linear and symmetric time-to-digital converter (TDC) which comprises: a first
input; a second input; a first delay line having a plurality of delay stages coupled together in …

An all-digital-phase-locked-loop (ADPLL) includes a digi tally controlled oscillator (DCO)
arranged to generate a DCO output signal, and a feedback loop comprising a set of …

A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an
example, of the present disclosure operates in a frequency tracking mode to adjust a …

Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital
controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital …

US10171089B2 - PVT-free calibration function using a doubler circuit for TDC resolution in
ADPLL applications - Google Patents US10171089B2 - PVT-free calibration function using …

A regulator system includes a multi-bit detector system and a multi-cell charge/discharge
circuit. The multi-bit detector system includes a plurality of detectors. Each of the plurality of …

US10230360B2 - Increasing resolution of on-chip timing uncertainty measurements -
Google Patents US10230360B2 - Increasing resolution of on-chip timing uncertainty …

Aspects of this disclosure relate to a digital phase-locked loop (DPLL) arranged to adjust
output phase using a phase adjustment signal. In certain embodiments, the phase …

A digital synthesizer is described that comprises: a ramp generator configured to generate a
signal of frequency control words (FCW), that describes a desired frequency modulated …

A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an
example, of the present disclosure operates in a frequency tracking mode to adjust a …