Some embodiments include an assembly having a memory stack which includes dielectric
levels and conductive levels. A select gate structure is over the memory stack. A trench …

A transistor includes a gate structure that has a first gate dielectric layer and a second gate
dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate …

US20220165563A1 - Method for providing doped silicon - Google Patents
US20220165563A1 - Method for providing doped silicon - Google Patents Method for …

A transistor includes a gate structure that has a first gate dielectric layer and a second gate
dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate …

H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or
switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier …

A finFET device includes a doped source and/or drain extension that is disposed between a
gate spacer of the finFET and a bulk semiconductor portion of the semicon ductor substrate …

Described herein is a method of depositing a plasma resistant ceramic coating onto a
surface of a chamber component using a non-line-of-sight (NLOS) deposition process, such …