Method and apparatus for high-speed input sampling
S Lee - US Patent 7,366,942, 2008 - Google Patents
2. Description of Related Art In modem high frequency integrated circuits, the valid data
window in which signal inputs are valid for sampling by a clock is continually shrinking as …
window in which signal inputs are valid for sampling by a clock is continually shrinking as …
Integrated circuit and method of asynchronously routing data in an integrated circuit
AS Kaviani - US Patent 8,294,490, 2012 - Google Patents
An integrated circuit enabling asynchronous data communication is disclosed. The
integrated circuit comprises a plurality of circuit blocks, each circuit block of the plurality of …
integrated circuit comprises a plurality of circuit blocks, each circuit block of the plurality of …
Logic synthesis of multi-level domino asynchronous pipelines
Methods and apparatus are described for optimizing a circuit design. A gate level circuit
description corresponding to the circuit design is generated. The gate level circuit …
description corresponding to the circuit design is generated. The gate level circuit …
Logic synthesis of multi-level domino asynchronous pipelines
4,875.224. A 10/1989 Simpson includes a plurality of pipelines across a plurality of levels.
49 1 23 48 A 3, 1990 Maki etal Using a linear programming technique, a minimal number of …
49 1 23 48 A 3, 1990 Maki etal Using a linear programming technique, a minimal number of …
Error recovery within processing stages of an integrated circuit
DT Blaauw, DM Bull, S Das - US Patent 7,320,091, 2008 - Google Patents
An integrated circuit includes a plurality of processing stages each including processing
logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture ele ment …
logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture ele ment …
Method and system for asynchronous chip design
KS Stevens - US Patent 8,065,647, 2011 - Google Patents
6,622,273 B1 9, 2003 Barnes replaced with a plurality of handshaking circuits. Data valid ity
is encoded into a communication path between a first pipeline stage and a second pipeline …
is encoded into a communication path between a first pipeline stage and a second pipeline …
Fault tolerant asynchronous circuits
R Manohar, CW Kelly - US Patent 7,504,851, 2009 - Google Patents
US7504851B2 - Fault tolerant asynchronous circuits - Google Patents US7504851B2 - Fault
tolerant asynchronous circuits - Google Patents Fault tolerant asynchronous circuits Download …
tolerant asynchronous circuits - Google Patents Fault tolerant asynchronous circuits Download …
System and method for determining airway obstruction
J Kline - US Patent App. 11/282,012, 2007 - Google Patents
A method and system for detecting the presence of restriction to expired airflow in humans or
animals by analyzing the expired capnogram and oxygram, as well as the geometric …
animals by analyzing the expired capnogram and oxygram, as well as the geometric …
Single event upset error detection within an integrated circuit
5, 291496 A 3, 1994 Andaleon et al. 7,594,150 B2 9/2009 Chakraborty et al. 5.313. 625 A 5,
1994 Hess etal 7,650,551 B2 1, 2010 Flautner et al. 5.33705 A 6, 1994 Gould et al …
1994 Hess etal 7,650,551 B2 1, 2010 Flautner et al. 5.33705 A 6, 1994 Gould et al …
Asynchronous digital circuits including arbitration and routing primitives for asynchronous and mixed-timing networks
SM Nowick, M Horak, M Carlberg - US Patent 8,362,802, 2013 - Google Patents
Asynchronous digital circuits are described, including arbi tration and routing primitives for
asynchronous and mixed timing networks. An asynchronous arbitration primitive has two …
asynchronous and mixed timing networks. An asynchronous arbitration primitive has two …