ReCycle: Pipeline adaptation to tolerate process variation
A Tiwari, SR Sarangi, J Torrellas - ACM SIGARCH Computer Architecture …, 2007 - dl.acm.org
Process variation affects processor pipelines by making some stages slower and others
faster, therefore exacerbating pipeline unbalance. This reduces the frequency attainable by …
faster, therefore exacerbating pipeline unbalance. This reduces the frequency attainable by …
Interconnection system
JCR Bennett - US Patent 8,726,064, 2014 - Google Patents
2021-06-16 Assigned to VSIP HOLDINGS LLC (F/K/A VIOLIN SYSTEMS LLC (F/K/A VIOLIN
MEMORY, INC.)) reassignment VSIP HOLDINGS LLC (F/K/A VIOLIN SYSTEMS LLC (F/K/A …
MEMORY, INC.)) reassignment VSIP HOLDINGS LLC (F/K/A VIOLIN SYSTEMS LLC (F/K/A …
Mitigating thermal effects on clock skew with dynamically adaptive drivers
On-chip temperature gradient emerged as a major design concern for high performance
integrated circuits for the current and future technology nodes. Clock skew is an undesirable …
integrated circuits for the current and future technology nodes. Clock skew is an undesirable …
Revisiting automated physical synthesis of high-performance clock networks
High-performance clock distribution has been a challenge for nearly three decades. During
this time, clock synthesis tools and algorithms have strove to address a myriad of important …
this time, clock synthesis tools and algorithms have strove to address a myriad of important …
mDTM: Multi-objective dynamic thermal management for on-chip systems
Thermal hot spots and unbalanced temperatures between cores on chip can cause either
degradation in performance or may have a severe impact on reliability, or both. In this paper …
degradation in performance or may have a severe impact on reliability, or both. In this paper …
Configurable interconnection system
JCR Bennett - US Patent 9,465,756, 2016 - Google Patents
An interconnection system, apparatus and method is described where the motherboard may
be populated with less than all of the modules that it has been designed to accept while …
be populated with less than all of the modules that it has been designed to accept while …
Interconnection system
JCR Bennett - US Patent 9,582,449, 2017 - Google Patents
2021-06-16 Assigned to VSIP HOLDINGS LLC (F/K/A VIOLIN SYSTEMS LLC (F/K/A VIOLIN
MEMORY, INC.)) reassignment VSIP HOLDINGS LLC (F/K/A VIOLIN SYSTEMS LLC (F/K/A …
MEMORY, INC.)) reassignment VSIP HOLDINGS LLC (F/K/A VIOLIN SYSTEMS LLC (F/K/A …
Catching the flu: Emerging threats from a third party power management unit
R JayashankaraShridevi, C Rajamanikkam… - Proceedings of the 53rd …, 2016 - dl.acm.org
Power management units (PMU) have come into the spotlight with energy efficiency
becoming a first order constraint in MPSoC designs. To cater to the exponential rise in …
becoming a first order constraint in MPSoC designs. To cater to the exponential rise in …
Impact of power supply voltage variations on FPGA-based digital systems performance
J Freijedo, L Costas, J Semião… - Journal of Low …, 2010 - ingentaconnect.com
Power Supply Noise (PSN) may be induced by environmental or operational conditions, and
has impact on digital systems performance. Field Programmable Gate Array (FPGA) vendors …
has impact on digital systems performance. Field Programmable Gate Array (FPGA) vendors …
AutoRex: An automated post-silicon clock tuning tool
D Tadesse, J Grodstein, RI Bahar - 2009 International Test …, 2009 - ieeexplore.ieee.org
Post-silicon clock-tuning is a technique used as part of speed-debug efforts to increase the
allowable clock frequency of a chip. These days, it is not uncommon for high-end …
allowable clock frequency of a chip. These days, it is not uncommon for high-end …