A variable threshold voltage hybrid evaluation network based dynamic XOR/XNOR gate is
presented to reduce the parameters leakage power dissipation, dynamic power, and layout …

This paper describes a novel method for reducing gate oxide and subthreshold leakage in
domino using Si Nano-materials. Between the silicon precharge transistor and the pull down …

This paper represents a novel ten transistor based static random access memory (SRAM)
architecture with high read noise margin for low power applications. The novel 10T SRAM …

A novel DOIND logic approach is proposed for domino logic, which reduces the leakage
current with a minimum delay penalty. Simulation is performed at 70 nm technology node …

Dual threshold voltages domino design methodology utilizes low threshold voltages for all
transistors that can switch during the evaluate mode and utilizes high threshold voltages for …

Purpose This paper aims to propose a new sleep signal controlled footless domino circuit for
reducing the subthreshold and gate oxide leakage currents. Design/methodology/approach …

We are moving into an era where large SoCs will have a portfolio of different kinds of cores
and accelerators. Many of these computational elements might be designed by third parties …

This thesis presents a novel thirteen transistor dynamic XOR/XNOR gate intended for
advanced microprocessor inbuilt arithmetic and logic unit (ALU). The objectives are to …

Standby switch can strongly turn off all the high threshold voltage transistors, which
enhances the effectiveness of a dual threshold voltage CMOS technology to reduce sub …