[HTML][HTML] State of the art and future perspectives in advanced CMOS technology
The international technology roadmap of semiconductors (ITRS) is approaching the
historical end point and we observe that the semiconductor industry is driving …
historical end point and we observe that the semiconductor industry is driving …
Nanomaterials in transistors: From high-performance to thin-film applications
AD Franklin - Science, 2015 - science.org
BACKGROUND Transistors are one of the most enabling “hidden” technologies of all time
and have facilitated the development of computers, the Internet, thin mobile displays, and …
and have facilitated the development of computers, the Internet, thin mobile displays, and …
Considerations for ultimate CMOS scaling
KJ Kuhn - IEEE transactions on Electron Devices, 2012 - ieeexplore.ieee.org
This review paper explores considerations for ultimate CMOS transistor scaling. Transistor
architectures such as extremely thin silicon-on-insulator and FinFET (and related …
architectures such as extremely thin silicon-on-insulator and FinFET (and related …
FinFET versus gate-all-around nanowire FET: Performance, scaling, and variability
Performance, scalability, and resilience to variability of Si SOI FinFETs and gate-all-around
(GAA) nanowires (NWs) are studied using in-house-built 3-D simulation tools. Two …
(GAA) nanowires (NWs) are studied using in-house-built 3-D simulation tools. Two …
[HTML][HTML] Atomic layer etching at the tipping point: an overview
GS Oehrlein, D Metzler, C Li - … Journal of Solid State Science and …, 2015 - iopscience.iop.org
The ability to achieve near-atomic precision in etching different materials when transferring
lithographically defined templates is a requirement of increasing importance for nanoscale …
lithographically defined templates is a requirement of increasing importance for nanoscale …
[HTML][HTML] A review of the gate-all-around nanosheet FET process opportunities
S Mukesh, J Zhang - Electronics, 2022 - mdpi.com
In this paper, the innovations in device design of the gate-all-around (GAA) nanosheet FET
are reviewed. These innovations span enablement of multiple threshold voltages and …
are reviewed. These innovations span enablement of multiple threshold voltages and …
Method of constructing a semiconductor device and structure
Z Or-Bach, DC Sekar, B Cronquist, I Beinglass… - US Patent …, 2012 - Google Patents
2011-12-06 Assigned to MONOLITHIC 3D INC. reassignment MONOLITHIC 3D INC.
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
Gate-all-around silicon nanowire 25-stage CMOS ring oscillators with diameter down to 3 nm
S Bangsaruntip, A Majumdar, GM Cohen… - 2010 symposium on …, 2010 - ieeexplore.ieee.org
We demonstrate the world's first top-down CMOS ring oscillators (ROs) fabricated with gate-
all-around (GAA) silicon nanowire (NW) FETs having diameters as small as 3 nm. NW …
all-around (GAA) silicon nanowire (NW) FETs having diameters as small as 3 nm. NW …
The evolution of scaling from the homogeneous era to the heterogeneous era
M Bohr - 2011 international electron devices meeting, 2011 - ieeexplore.ieee.org
Traditional MOSFET scaling served our industry well for more than three decades by
providing continuous improvements in transistor performance, power and cost. This was the …
providing continuous improvements in transistor performance, power and cost. This was the …
[HTML][HTML] Vertical silicon nanowire field effect transistors with nanoscale gate-all-around
Y Guerfi, G Larrieu - Nanoscale research letters, 2016 - Springer
Nanowires are considered building blocks for the ultimate scaling of MOS transistors,
capable of pushing devices until the most extreme boundaries of miniaturization thanks to …
capable of pushing devices until the most extreme boundaries of miniaturization thanks to …