Write me and I'll tell you secrets–write-after-write effects on Intel CPUs
There is a long history of side channels in the memory hierarchy of modern CPUs.
Especially the cache side channel is widely used in the context of transient execution attacks …
Especially the cache side channel is widely used in the context of transient execution attacks …
{SCARF}–A {Low-Latency} Block Cipher for Secure {Cache-Randomization}
Randomized cache architectures have proven to significantly increase the complexity of
contention-based cache side channel attacks and therefore present an important building …
contention-based cache side channel attacks and therefore present an important building …
Risky translations: Securing tlbs against timing side channels
Microarchitectural side-channel vulnerabilities in modern processors are known to be a
powerful attack vector that can be utilized to bypass common security boundaries like …
powerful attack vector that can be utilized to bypass common security boundaries like …
Prune+ PlumTree-Finding Eviction Sets at Scale
T Kessous, N Gilboa - 2024 IEEE Symposium on Security and Privacy …, 2024 - computer.org
Finding eviction sets for a large fraction of the cache is an essential preprocessing step for
Prime+ Probe based cache side-channel attacks. Previous work on this problem reduces it …
Prime+ Probe based cache side-channel attacks. Previous work on this problem reduces it …
On The Effect of Replacement Policies on The Security of Randomized Cache Architectures
Randomizing the mapping of addresses to cache entries has proven to be an effective
technique for hardening caches against contention-based attacks like Prime+ Prome. While …
technique for hardening caches against contention-based attacks like Prime+ Prome. While …
FlushTime: Towards Mitigating Flush-based Cache Attacks via Collaborating Flush Instructions and Timers on ARMv8-A
ARMv8-A processors generally utilize optimization techniques such as multi-layer cache, out-
of-order execution and branch prediction to improve performance. These optimization …
of-order execution and branch prediction to improve performance. These optimization …
One more set: Mitigating conflict-based cache side-channel attacks by extending cache set
Caches are vulnerable to side-channel attacks as a type of shared hardware resource. Most
existing defense methods can be categorized into two categories: partition and …
existing defense methods can be categorized into two categories: partition and …
NVM-Flip: Non-Volatile-Memory BitFlips on the System Level
Emerging non-volatile memories (NVMs), such as spin-torque transfer memory (STT-
RAM/MRAM)[36], phase-change random access memory (PCRAM)[14], or redox-based …
RAM/MRAM)[36], phase-change random access memory (PCRAM)[14], or redox-based …
Basicblocker: Isa redesign to make spectre-immune cpus faster
Recent research has revealed an ever-growing class of microarchitectural attacks that
exploit speculative execution, a standard feature in modern processors. Proposed and …
exploit speculative execution, a standard feature in modern processors. Proposed and …
BackCache: Mitigating contention-based cache timing attacks by hiding cache line evictions
Caches are used to reduce the speed differential between the CPU and memory to improve
the performance of modern processors. However, attackers can use contention-based cache …
the performance of modern processors. However, attackers can use contention-based cache …