Performance and power constraints come together with Complementary Metal Oxide
Semiconductor technology scaling in future Exascale systems. Technology scaling makes …

We present here a report produced by a workshop on 'Addressing failures in exascale
computing'held in Park City, Utah, 4–11 August 2012. The charter of this workshop was to …

Single-event upsets from particle strikes have become a key challenge in microprocessor
design. Techniques to deal with these transients faults exist, but come at a cost. Designers …

To improve performance and reduce power, processor designers employ advances that
shrink feature sizes, lower voltage levels, reduce noise margins, and increase clock rates …

Smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise
margins make future generations of microprocessors increasingly prone to transient …

Architecture Design for Soft Errors provides a comprehensive description of the architectural
techniques to tackle the soft error problem. It covers the new methodologies for quantitative …

Exponential growth in the number of on-chip transistors, coupled with reductions in voltage
levels, makes each generation of microprocessors increasingly vulnerable to transient faults …

Radiation-induced soft errors have emerged as a key challenge in computer system design.
If the industry is to continue to provide customers with the level of reliability they expect …

To address the increasing susceptibility of commodity chip multiprocessors (CMPs) to
transient faults, we propose Chiplevel Redundantly Threaded multiprocessor with Recovery …

We have developed Argus, a novel approach for providing low-cost, comprehensive error
detection for simple cores. The key to Argus is that the operation of a von Neumann core …