The memory wall continues to limit the performance of modern out-of-order (OOO)
processors, despite the expensive provisioning of large multi-level caches and …

Load instructions often limit instruction-level parallelism (ILP) in modern processors due to
data and resource dependences they cause. Prior techniques like Load Value Prediction …

The computing landscape has been increasingly characterized by processor architectures
with increasing core counts, while a majority of the software applications remain inherently …

当今的处理器性能与存储器带宽和延迟严重失衡的问题限制了计算系统的整体性能,
而存储器的性能对制程工艺不敏感, 在后摩尔时代下很难再通过集成电路制造工艺的迭代获得 …

Accurate simulation techniques are indispensable to efficiently propose new memory or
architectural organizations. As implementing new hardware concepts in real systems is often …

Value prediction is a microarchitectural technique that enhances processor performance by
speculatively breaking true data dependencies. It has demonstrated improved performance …

The direction of conditional branches is predicted correctly in modern processors with great
accuracy. We find several instructions in the dynamic instruction stream that contribute only …

Accurate simulation techniques are indispensable to efficiently propose new memory or
architectural organizations. As implementing new hardware concepts in real systems is often …