Investigation on different ESD protection strategies devoted to 3.3 V RF applications (2 GHz) in a 0.18/spl mu/m CMOS process
C Richier, P Salome, G Mabboux, I Zaza… - … 2000 (IEEE Cat. No …, 2000 - ieeexplore.ieee.org
ESD protection for RF applications must deal with good ESD performance, minimum
capacitance, zero series resistance and good capacitance linearity. In order to fulfil these …
capacitance, zero series resistance and good capacitance linearity. In order to fulfil these …
An improved electrostatic discharge protection structure for reducing triggering voltage and parasitic capacitance
X Gao, JJ Liou, W Wong, S Vishwanathan - Solid-State Electronics, 2003 - Elsevier
On-chip electrostatic discharge (ESD) protection structures are frequently used in microchips
to protect the core circuit again ESD damages. Relatively large parasitic capacitances …
to protect the core circuit again ESD damages. Relatively large parasitic capacitances …
Investigation of the gate-driven effect and substrate-triggered effect on ESD robustness of CMOS devices
TY Chen, MD Ker - IEEE Transactions on Device and Materials …, 2001 - ieeexplore.ieee.org
The gate-driven effect and substrate-triggered effect on electrostatic discharge (ESD)
robustness of CMOS devices are measured and compared in this paper. The operation …
robustness of CMOS devices are measured and compared in this paper. The operation …
Substrate pump NMOS for ESD protection applications
C Duvvury, S Ramaswamy… - … 2000 (IEEE Cat. No …, 2000 - ieeexplore.ieee.org
The use of a substrate pump to achieve uniform npn protection in a multi-finger NMOS is
reported for advanced CMOS technologies with silicide. The novel feature of this device …
reported for advanced CMOS technologies with silicide. The novel feature of this device …
Compact modeling of on-chip ESD protection devices using Verilog-A
J Li, S Joshi, R Barnes… - IEEE Transactions on …, 2006 - ieeexplore.ieee.org
A practical approach for the compact modeling of electrostatic discharge (ESD) protection
devices, using the behavioral language Verilog-A, is presented. Models of the NMOS …
devices, using the behavioral language Verilog-A, is presented. Models of the NMOS …
Self-substrate-triggered technique to enhance turn-on uniformity of multi-finger ESD protection devices
MD Ker, JH Chen - IEEE journal of solid-state circuits, 2006 - ieeexplore.ieee.org
A novel self-substrate-triggered technique for on-chip ESD protection design is proposed to
solve the non-uniform turn-on phenomenon of multi-finger gate-grounded nMOS (GGnMOS) …
solve the non-uniform turn-on phenomenon of multi-finger gate-grounded nMOS (GGnMOS) …
Analysis of nonuniform ESD current distribution in deep submicron NMOS transistors
KH Oh, C Duvvury, K Banerjee… - IEEE Transactions on …, 2002 - ieeexplore.ieee.org
This paper presents a detailed study of the nonuniform bipolar conduction phenomenon
under electrostatic discharge (ESD) events in single-finger NMOS transistors and analyzes …
under electrostatic discharge (ESD) events in single-finger NMOS transistors and analyzes …
Correlating drain junction scaling, salicide thickness, and lateral NPN behavior, with the ESD/EOS performance of a 0.25/spl mu/m CMOS process
A Amerasekera, V McNeil… - … Electron Devices Meeting …, 1996 - ieeexplore.ieee.org
In this paper we show for the first time, how junction depths and salicide thicknesses in a
0.25/spl mu/m CMOS process affect the current gain/spl beta/of a self-biased lateral NPN …
0.25/spl mu/m CMOS process affect the current gain/spl beta/of a self-biased lateral NPN …
Latch-up in 65nm CMOS technology: a scaling perspective
In this study, through a detailed analysis of the last four CMOS technology nodes, targeting
similar applications, the intrinsic latch-up process sensitivity is investigated in an attempt to …
similar applications, the intrinsic latch-up process sensitivity is investigated in an attempt to …
Design methodology and optimization of gate-driven NMOS ESD protection circuits in submicron CMOS processes
JZ Chen, EA Amerasekera… - IEEE Transactions on …, 1998 - ieeexplore.ieee.org
This paper describes the design methodology for gate driven NMOS ESD protection in
submicron CMOS processes. A new PNP Driven NMOS (PDNMOS)-protection scheme is …
submicron CMOS processes. A new PNP Driven NMOS (PDNMOS)-protection scheme is …