Robust and low-power digitally programmable delay element designs employing neuron-MOS mechanism
R Zhang, M Kaneko - ACM Transactions on Design Automation of …, 2015 - dl.acm.org
The feasibility of designing digitally programmable delay elements (PDEs) employing
neuron-MOS mechanism is investigated in this work. By coupling the capacitors on the gate …
neuron-MOS mechanism is investigated in this work. By coupling the capacitors on the gate …
Clock buffer
V Sharma, RIMP Meijer, JP de Gyvez - US Patent 9,065,439, 2015 - Google Patents
A tuneable buffer circuit for use in a clock tree has multiple buffers in parallel, each buffer
having a grounding function, and also a bypass switch in parallel with the buffers. The circuit …
having a grounding function, and also a bypass switch in parallel with the buffers. The circuit …
Clock Power Reduction Using NDR Routing
S Alure, N Ramavankateswaran, R Buddi… - Proceeding of Fifth …, 2021 - Springer
The recent advancement in nanotechnology over a different scope of industries and an
expanded microelectronics market demand for low power, high performance and complexity …
expanded microelectronics market demand for low power, high performance and complexity …
Self-adjusting mechanism to dynamically suppress the effect of PVT variations on clock skew
TT Lin, WP Tu, SH Huang - 2014 IEEE Asia Pacific Conference …, 2014 - ieeexplore.ieee.org
Clock skew minimization is an important topic in the design of synchronous sequential
circuit. As the process technology scaling, the effect of process/voltage/temperature (PVT) …
circuit. As the process technology scaling, the effect of process/voltage/temperature (PVT) …
Bounded and Variation-Aware Design for Clock Tree Synthesis
SP Lerner - 2024 - search.proquest.com
As semiconductor technology continues to advance at an unprecedented pace, the
integration of smaller and more densely packed transistors on silicon wafers has ushered in …
integration of smaller and more densely packed transistors on silicon wafers has ushered in …
High performance clock path elements for clock skew reduction
S Ravi, S Trehan, M Jain… - 2019 2nd international …, 2019 - ieeexplore.ieee.org
this paper is presenting the findings of project work that involves finding more efficient and
faster circuit logics to bring down the clock skew. Clock skew is the instantaneous difference …
faster circuit logics to bring down the clock skew. Clock skew is the instantaneous difference …
PVT-variations-tolerant clock design using self-correcting adjustable delay buffers
WP Tu, SH Huang, HH Lu - 2014 International Symposium on …, 2014 - ieeexplore.ieee.org
As the process technology scaling, the tolerance to PVT (process/voltage/temperature)
variation has become a serious concern. During the post-silicon stage, ADBs (adjustable …
variation has become a serious concern. During the post-silicon stage, ADBs (adjustable …
新的動態時序差異控制機制及其可調式延遲緩衝器設計
張嘉文 - 中原大學電子工程學系學位論文, 2018 - airitilibrary.com
時序差異的最小化對於序向時序最佳化來說是非常重要的任務. 隨著製程技術的進步, 製程變異,
電壓變異和溫度變異所引起的時序差異可能會導致嚴重的問題, 這些無法預先得知的因素 …
電壓變異和溫度變異所引起的時序差異可能會導致嚴重的問題, 這些無法預先得知的因素 …
Skew Analysis on Multisource Clock Tree Synthesis Using H-Tree Structure
VK Bhat, HH Surendra, HR Archana - Advances in Communication, Signal …, 2019 - Springer
The most critical constraints in System on chip (SoC's), to determine the performance are
area and power. As technology scales down, innovative clock tree design techniques are …
area and power. As technology scales down, innovative clock tree design techniques are …
A Mechanism for Adjustable-Delay-Buffer Selection to Dynamically Control Clock Skew
CW Chang, SH Huang - 2018 International Conference on …, 2018 - ieeexplore.ieee.org
Clock skew minimization is a very important task for sequential timing optimization. As the
technology node continues to shrink, the clock skew caused by the effects of …
technology node continues to shrink, the clock skew caused by the effects of …