Gem5+ rtl: A framework to enable rtl models inside a full-system simulator

G López-Paradís, A Armejach, M Moretó - Proceedings of the 50th …, 2021 - dl.acm.org
In recent years there has been a surge of interest in designing custom accelerators for
power-efficient high-performance computing. However, available tools to simulate low-level …

Paas: A system level simulator for heterogeneous computing architectures

T Liang, L Feng, S Sinha… - 2017 27th International …, 2017 - ieeexplore.ieee.org
Heterogeneous computing with hardware accelerators is a promising direction to overcome
the power and performance walls in traditional computing systems. CPU-accelerator …

A practical view of the state-of-the-art of lattice-based cryptanalysis

A Mariano, T Laarhoven, F Correia, M Rodrigues… - Ieee …, 2017 - ieeexplore.ieee.org
This paper describes the lattice problems that are key in the study of lattice-based
cryptography, identifies and categorizes methods for solving these problems, analyzes …

Hardware accelerator for wearable and portable radar-based microwave breast imaging systems

I Saied, T Arslan, R Ullah, C Liu… - 2021 IEEE International …, 2021 - ieeexplore.ieee.org
This paper proposes a novel hardware accelerator for wearable and portable radar-based
microwave breast imaging applications. The hardware accelerator is implemented on a low …

ERAS: A Flexible and Scalable Framework for Seamless Integration of RTL Models with Structural Simulation Toolkit

S Nema, SK Chunduru, C Kodigal… - 2023 IEEE …, 2023 - ieeexplore.ieee.org
The prevalence of custom Intellectual Properties (IPs) poses challenges for assessing their
system-level performance and functional behavior. Register Transfer Level (RTL) simulation …

A combined fast/cycle accurate simulation tool for reconfigurable accelerator evaluation: application to distributed data management

E Lenormand, T Goubier, L Cudennec… - … Workshop on Rapid …, 2020 - ieeexplore.ieee.org
Parallel computing systems based on reconfigurable accelerators are becoming (1)
increasingly heterogeneous,(2) difficult to design and (3) complex to model. Such modeling …

On the simulation of processors enhanced for security in virtualization

SC Mhatre, P Chandran - Companion of the 2018 ACM/SPEC …, 2018 - dl.acm.org
Computer system simulators model the hardware and reduce the time required for the
design of the hardware, by exploring the design space and thereby eliminating the time …

Evaluating ARM and RISC-V Architectures For High-Performance Computing With Docker and Kubernetes

V Dakić, L Mršić, Z Kunić, G Đambić - 2024 - preprints.org
This paper thoroughly assesses the ARM and RISC-V architectures in the context of High-
Performance Computing (HPC). It includes an analysis of Docker, Kubernetes, and KVM …

Simacc: A configurable cycle-accurate simulator for customized accelerators on cpu-fpgas socs

K Iordanou, O Palomar, J Mawer… - 2019 IEEE 27th …, 2019 - ieeexplore.ieee.org
This paper describes a flexible infrastructure for fast computer architecture simulation and
prototyping of accelerator IP. A trend for System-on-Chips is to include application specific …

[图书][B] Efficient Simulation Methodologies for System-Level Performance Exploration and Reliability Analysis of Hardware Designs

S Nema - 2023 - search.proquest.com
Abstract As custom Intellectual Properties (IPs) have become prevalent along with transistor
scaling to improve performance, evaluating the performance of these IPs at the system level …