Design and implementation of turbo coder for 5G technology
S Joseph, R Kirubakkar… - 2021 7th International …, 2021 - ieeexplore.ieee.org
An error could have occurred at the recipient end around a communication system once text
is read from intermediate nodes. The Turbo Coder is used to get the originally transmitted …
is read from intermediate nodes. The Turbo Coder is used to get the originally transmitted …
Design of Low-Power Turbo Coder for Low-Energy Mobile Communications
Mobile Communication systems use turbo codes for correcting errors. As compared to other
error correction codes, turbo codes provide great error correcting capabilities. The design of …
error correction codes, turbo codes provide great error correcting capabilities. The design of …
Realization of turbo decoder on coarse grained reconfigurable architectures
S Sekhar, Y Gopinathan, B Yamuna… - 2022 IEEE 19th India …, 2022 - ieeexplore.ieee.org
Error correcting codes such as turbo codes are incorporated in present-day wireless and
satellite communication systems for error free data transmission. Conventional turbo …
satellite communication systems for error free data transmission. Conventional turbo …
VLSI Implementation of Turbo Product Code
N Varghese, S Murugan - 2021 Second International …, 2021 - ieeexplore.ieee.org
Turbo product code (TPC) is a special type of parallel concatenation of convolution codes.
The length of convolution code can be altered using TPC. They can be used as forward error …
The length of convolution code can be altered using TPC. They can be used as forward error …
[PDF][PDF] Turbo encoder and decoder chip design and FPGA device analysis for communication system
A Devrari, A Kumar - Int J Reconfigurable & Embedded Syst ISSN - academia.edu
Turbo codes are error-correcting codes with performance that is close to the Shannon
theoretical limit (SHA). The motivation for using turbo codes is that the codes are an …
theoretical limit (SHA). The motivation for using turbo codes is that the codes are an …
Low Power 90 nm 8× 4 Pseudo NMOS Barrel Shifter Design
JSD Vudatha, SP Rajeev… - 2021 5th International …, 2021 - ieeexplore.ieee.org
In this paper, the authors implemented an 8× 4 barrel shifter using two MOS logics: static
CMOS and pseudo NMOS. Cadence Virtuoso is used for simulation at 90nm technology …
CMOS and pseudo NMOS. Cadence Virtuoso is used for simulation at 90nm technology …
VLSI Design of Low Power Barrel Shifter using 90 nm TG technology
JSD Vudatha, N Kota, P Gutha… - … , Signals & Systems …, 2021 - ieeexplore.ieee.org
The barrel shifter is known for the manipulation of various bits in a single clock cycle. In this
paper, an 8*4 barrel shifter is designed using transmission gate technology. The design and …
paper, an 8*4 barrel shifter is designed using transmission gate technology. The design and …
[DOC][DOC] SoC Based Analysis and Implementation of Turbo codes with puncturing.
The chip level implementation of error detection and correction codes is a challenging
aspect for VLSI systems as the system complexity often makes it infeasible for systems to be …
aspect for VLSI systems as the system complexity often makes it infeasible for systems to be …