Record Maximum Transconductance of 3.45 mS/ for III-V FETs
This letter presents a self-aligned InGaAs quantum-well MOSFET with a transconductance,
gm, max, of 3.45 mS/μm at V ds= 0.5 V. This is a record value among III-V FETs of any kind …
gm, max, of 3.45 mS/μm at V ds= 0.5 V. This is a record value among III-V FETs of any kind …
III-V/Ge MOS device technologies for low power integrated systems
CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of the
promising devices for high performance and low power integrated systems in the future …
promising devices for high performance and low power integrated systems in the future …
High Performance Tri-Gate Extremely Thin-Body InAs-On-Insulator MOSFETs With High Short Channel Effect Immunity and Tunability
We have investigated the effects of the tri-gate channel structure on electrical properties of
extremely thin-body (ETB) InAs-on-insulator (-OI) MOSFETs. It was found that the tri-gate …
extremely thin-body (ETB) InAs-on-insulator (-OI) MOSFETs. It was found that the tri-gate …
Ultra-high aspect ratio InP junctionless FinFETs by a novel wet etching method
Junctionless FinFETs with an array of ultra-high aspect ratio (HAR) fins, enabled by inverse
metal-assisted chemical etching, are developed to achieve high on-current per fin. The …
metal-assisted chemical etching, are developed to achieve high on-current per fin. The …
Positive bias instability and recovery in InGaAs channel nMOSFETs
Instability of InGaAs channel nMOSFETs with the Al 2 O 3/ZrO 2 gate stack under positive
bias stress demonstrates recoverable and unrecoverable components, which can be …
bias stress demonstrates recoverable and unrecoverable components, which can be …
[PDF][PDF] Highly scalable raised source/drain InAs quantum well MOSFETs exhibiting ION= 482 µ A/µ m at IOFF= 100 nA/µ m and VDD= 0.5 V
S Lee, CY Huang, D Cohen-Elias… - … Electron Device Lett, 2014 - academia.edu
We report raised source/drain (S/D) InAs quantum well MOSFETs incorporating a vertical
spacer formed by metal–organic chemical vapor deposition epitaxial regrowth. By adopting …
spacer formed by metal–organic chemical vapor deposition epitaxial regrowth. By adopting …
Performance Benchmarking and Effective Channel Length for Nanoscale InAs, , and sSi n-MOSFETs
D Lizzit, D Esseni, P Palestri… - IEEE transactions on …, 2014 - ieeexplore.ieee.org
Thanks to the high electron velocities, III-V semiconductors have the potential to meet the
challenging ITRS requirements for high performance for sub-22-nm technology nodes and …
challenging ITRS requirements for high performance for sub-22-nm technology nodes and …
In0.53Ga0.47As-Based nMOSFET Design for Low Standby Power Applications
KK Bhuwalka, Z Wu, HK Noh, W Lee… - … on Electron Devices, 2015 - ieeexplore.ieee.org
III–V n-channel MOSFETs based on In x Ga 1− x As are evaluated for low-power (LP)
technology at a sub-10-nm technology node. Aggressive design rules are followed, while …
technology at a sub-10-nm technology node. Aggressive design rules are followed, while …
In0.53Ga0.47As-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors Utilizing Y2O3 Buried Oxide
In this letter, we have investigated electrical properties of metal-oxide-semiconductor (MOS)
gate stack of Pt/Y 2 O 3/In 0.53 Ga 0.47 As under different annealing conditions. We have …
gate stack of Pt/Y 2 O 3/In 0.53 Ga 0.47 As under different annealing conditions. We have …
Method and structure for III-V FinFET
E Leobandung - US Patent 9,496,379, 2016 - Google Patents
BACKGROUND The exemplary embodiments of this invention relate generally to
semiconductor devices and, more specifically, to semiconductor devices having channel …
semiconductor devices and, more specifically, to semiconductor devices having channel …