The worst-case execution-time problem—overview of methods and survey of tools
R Wilhelm, J Engblom, A Ermedahl, N Holsti… - ACM Transactions on …, 2008 - dl.acm.org
The determination of upper bounds on execution times, commonly called worst-case
execution times (WCETs), is a necessary step in the development and validation process for …
execution times (WCETs), is a necessary step in the development and validation process for …
A survey of computer architecture simulation techniques and tools
Computer architecture simulators play an important role in advancing computer architecture
research. With wider research directions and the increased number of simulators that have …
research. With wider research directions and the increased number of simulators that have …
Aladdin: A pre-rtl, power-performance accelerator simulator enabling large design space exploration of customized architectures
Hardware specialization, in the form of accelerators that provide custom datapath and
control for specific algorithms and applications, promises impressive performance and …
control for specific algorithms and applications, promises impressive performance and …
Razor: A low-power pipeline based on circuit-level timing speculation
With increasing clock frequencies and silicon integration, power aware computing has
become a critical concern in the design of embedded processors and systems-on-chip. One …
become a critical concern in the design of embedded processors and systems-on-chip. One …
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip
communication was frequently ignored. This was because of fast, single-cycle on-chip …
communication was frequently ignored. This was because of fast, single-cycle on-chip …
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
MMK Martin, DJ Sorin, BM Beckmann… - ACM SIGARCH …, 2005 - dl.acm.org
The Wisconsin Multifacet Project has created a simulation toolset to characterize and
evaluate the performance of multiprocessor hardware systems commonly used as database …
evaluate the performance of multiprocessor hardware systems commonly used as database …
A survey on coarse-grained reconfigurable architectures from a performance perspective
With the end of both Dennard's scaling and Moore's law, computer users and researchers
are aggressively exploring alternative forms of computing in order to continue the …
are aggressively exploring alternative forms of computing in order to continue the …
3D-stacked memory architectures for multi-core processors
GH Loh - ACM SIGARCH computer architecture news, 2008 - dl.acm.org
Three-dimensional integration enables stacking memory directly on top of a microprocessor,
thereby significantly reducing wire delay between the two. Previous studies have examined …
thereby significantly reducing wire delay between the two. Previous studies have examined …
Graphite: A distributed parallel simulator for multicores
This paper introduces the Graphite open-source distributed parallel multicore simulator
infrastructure. Graphite is designed from the ground up for exploration of future multi-core …
infrastructure. Graphite is designed from the ground up for exploration of future multi-core …
Design space exploration for 3D architectures
As technology scales, interconnects have become a major performance bottleneck and a
major source of power consumption for microprocessors. Increasing interconnect costs …
major source of power consumption for microprocessors. Increasing interconnect costs …