The worst-case execution-time problem—overview of methods and survey of tools

R Wilhelm, J Engblom, A Ermedahl, N Holsti… - ACM Transactions on …, 2008 - dl.acm.org
The determination of upper bounds on execution times, commonly called worst-case
execution times (WCETs), is a necessary step in the development and validation process for …

A survey of computer architecture simulation techniques and tools

A Akram, L Sawalha - Ieee Access, 2019 - ieeexplore.ieee.org
Computer architecture simulators play an important role in advancing computer architecture
research. With wider research directions and the increased number of simulators that have …

Aladdin: A pre-rtl, power-performance accelerator simulator enabling large design space exploration of customized architectures

YS Shao, B Reagen, GY Wei, D Brooks - ACM SIGARCH Computer …, 2014 - dl.acm.org
Hardware specialization, in the form of accelerators that provide custom datapath and
control for specific algorithms and applications, promises impressive performance and …

Razor: A low-power pipeline based on circuit-level timing speculation

D Ernst, NS Kim, S Das, S Pant, R Rao… - … . 36th Annual IEEE …, 2003 - ieeexplore.ieee.org
With increasing clock frequencies and silicon integration, power aware computing has
become a critical concern in the design of embedded processors and systems-on-chip. One …

GARNET: A detailed on-chip network model inside a full-system simulator

N Agarwal, T Krishna, LS Peh… - 2009 IEEE international …, 2009 - ieeexplore.ieee.org
Until very recently, microprocessor designs were computation-centric. On-chip
communication was frequently ignored. This was because of fast, single-cycle on-chip …

Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset

MMK Martin, DJ Sorin, BM Beckmann… - ACM SIGARCH …, 2005 - dl.acm.org
The Wisconsin Multifacet Project has created a simulation toolset to characterize and
evaluate the performance of multiprocessor hardware systems commonly used as database …

A survey on coarse-grained reconfigurable architectures from a performance perspective

A Podobas, K Sano, S Matsuoka - IEEE Access, 2020 - ieeexplore.ieee.org
With the end of both Dennard's scaling and Moore's law, computer users and researchers
are aggressively exploring alternative forms of computing in order to continue the …

3D-stacked memory architectures for multi-core processors

GH Loh - ACM SIGARCH computer architecture news, 2008 - dl.acm.org
Three-dimensional integration enables stacking memory directly on top of a microprocessor,
thereby significantly reducing wire delay between the two. Previous studies have examined …

Graphite: A distributed parallel simulator for multicores

JE Miller, H Kasture, G Kurian… - HPCA-16 2010 The …, 2010 - ieeexplore.ieee.org
This paper introduces the Graphite open-source distributed parallel multicore simulator
infrastructure. Graphite is designed from the ground up for exploration of future multi-core …

Design space exploration for 3D architectures

Y Xie, GH Loh, B Black, K Bernstein - ACM Journal on Emerging …, 2006 - dl.acm.org
As technology scales, interconnects have become a major performance bottleneck and a
major source of power consumption for microprocessors. Increasing interconnect costs …