Green and highly efficient MIMO transceiver system for 5G heterogenous networks
YIA Al-Yasir, AM Abdulkhaleq… - IEEE Transactions …, 2021 - ieeexplore.ieee.org
The paper presents the general requirements and an exemplary design of the RF front-end
system that in today's handset is a key consumer of power. The design is required to …
system that in today's handset is a key consumer of power. The design is required to …
A 0.002-mm 6.4-mW 10-Gb/s Full-Rate Direct DFE Receiver With 59.6% Horizontal Eye Opening Under 23.3-dB Channel Loss at Nyquist Frequency
This paper reports a full-rate direct decision-feedback-equalization (DFE) receiver with
circuit techniques to widen the data eye opening with competitive power and area …
circuit techniques to widen the data eye opening with competitive power and area …
A 0.8-to-6.5 Gb/s continuous-rate reference-less digital CDR with half-rate common-mode clock-embedded signaling
This paper presents a continuous-rate reference-less clock and data recovery (CDR) circuit
that utilizes common-mode clock-embedded signaling (CM-CES) and injection locking …
that utilizes common-mode clock-embedded signaling (CM-CES) and injection locking …
A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM-4 Receiver With a Jitter Compensation CDR
This article presents a four-level pulse amplitude modulation (PAM-4) receiver (Rx) with a
jitter compensation clock and data recovery (JCCDR) for high-speed retimer application …
jitter compensation clock and data recovery (JCCDR) for high-speed retimer application …
A 2.56-Gb/s serial wireline transceiver that supports an auxiliary channel in 65-nm CMOS
In this article, an asynchronous serial transceiver that is capable of transmitting and
receiving an auxiliary data stream concurrently with the primary data stream is described …
receiving an auxiliary data stream concurrently with the primary data stream is described …
A 2.2-pJ/bit 10-Gb/s forwarded-clock serial-link transceiver for IoE applications
M El-Badry, M El-Fiky, A Yasser… - … on Signals, Circuits …, 2017 - ieeexplore.ieee.org
This paper presents a 10-Gb/s power-efficient serial-link transceiver for the Internet-of-
Everything applications. The proposed transceiver employs several techniques to reduce …
Everything applications. The proposed transceiver employs several techniques to reduce …
A 2.56 Gbps serial wireline transceiver that supports an auxiliary channel and a hybrid line driver to compensate large channel loss
X Wang - 2020 - scholar.smu.edu
A 2.56 Gbps Serial Wireline Transceiver that Supports An Auxiliary Channel and A Hybrid
Line Driver to Compensate Large Channel Page 1 Southern Methodist University SMU …
Line Driver to Compensate Large Channel Page 1 Southern Methodist University SMU …
Power model analysis using variable rate clock network in CMOS processor
TJ Titus, V Vijayakumari, B Saranya… - Proceedings of the 7th …, 2016 - dl.acm.org
In this paper, we present a variable node clock network and a power model to estimate
leakage power in CMOS processor. Design of clock delivery network is a constrained …
leakage power in CMOS processor. Design of clock delivery network is a constrained …