Single bit line accessed high‐performance ultra‐low voltage operating 7T static random access memory cell with improved read stability
Static random access memory (SRAM) bit cell is a prominent element for portable devices.
The popularity of sleek designs and demand for longer battery life has driven memory cell …
The popularity of sleek designs and demand for longer battery life has driven memory cell …
E2CNNs: Ensembles of Convolutional Neural Networks to Improve Robustness Against Memory Errors in Edge-Computing Devices
To reduce energy consumption, it is possible to operate embedded systems at sub-nominal
conditions (eg, reduced voltage, limited eDRAM refresh rate) that can introduce bit errors in …
conditions (eg, reduced voltage, limited eDRAM refresh rate) that can introduce bit errors in …
A 16-kB 65-nm GC-eDRAM Macro With Internal Bias Voltage Generation Providing Over 100-s Retention Time
O Harel, A Yigit, E Feifel, R Giterman… - IEEE Journal of Solid …, 2024 - ieeexplore.ieee.org
Gain-cell embedded dynamic random access memory (GC-eDRAM) has emerged as a
suitable choice for embedded memory implementation due to its high density, low leakage …
suitable choice for embedded memory implementation due to its high density, low leakage …
Pseudo-Static Gain Cell of Embedded DRAM for Processing-in-Memory in Intelligent IoT Sensor Nodes
S Kim, JE Park - Sensors, 2022 - mdpi.com
This paper presents a pseudo-static gain cell (PS-GC) with extended retention time for an
embedded dynamic random-access memory (eDRAM) macro for analog processing-in …
embedded dynamic random-access memory (eDRAM) macro for analog processing-in …
FinFET based ultra-low power 3T GC-eDRAM with very high retention time in sub-22 nm
B Seyedzadeh Sany, B Ebrahimi - Analog Integrated Circuits and Signal …, 2022 - Springer
This paper presents an ultra-low power 3T gain-cell embedded DRAM (GC-eDRAM) cell in
fin field-effect transistor (FinFET). This memory structure uses fast and low leakage FinFET …
fin field-effect transistor (FinFET). This memory structure uses fast and low leakage FinFET …
Refresh algorithm for ensuring 100% memory availability in gain-cell embedded DRAM macros
R Golman, N Nachum, T Cohen, R Giterman… - IEEE …, 2021 - ieeexplore.ieee.org
Gain-cell embedded DRAM (GC-eDRAM) is a dense, low power option for embedded
memory implementation, supporting low supply voltages; however, it suffers from limited …
memory implementation, supporting low supply voltages; however, it suffers from limited …
A 1‐GHz GC‐eDRAM in 7‐nm FinFET with static retention time at 700 mV for ultra‐low power on‐chip memory applications
B Seyedzadeh Sany, B Ebrahimi - International Journal of …, 2022 - Wiley Online Library
Conventional static random‐access memory (SRAM) suffers from high leakage power in
advanced complementary metal‐oxide‐semiconductor nodes. Meanwhile, gain‐cell …
advanced complementary metal‐oxide‐semiconductor nodes. Meanwhile, gain‐cell …
A Comprehensive Review and Performance Analysis of Different 7T and 9T SRAM Bit Cells
In the given paper, the performance and durability of two 9T SRAM cells, namely 9T-1 and
9T-2 with two 7T SRAM cells, namely 7T-1 and 7T-2 are examined and then contrasted …
9T-2 with two 7T SRAM cells, namely 7T-1 and 7T-2 are examined and then contrasted …
ErgoDEC: A Fault Tolerant 28 nm LDPC Decoder Providing Stable FER Quality with Unreliable Memories
Communication systems have been associated with an inherent fault tolerance to hardware
reliability issues. Therefore, many publications have studied the impact of such issues on, for …
reliability issues. Therefore, many publications have studied the impact of such issues on, for …
Design of Low Power Gain-Cell eDRAM for 4Kb Memory Array in 130nm CMOS
Gain-cell (GC) embedded dynamic random-access memory (eDRAM) provides high density,
low leakage power, small size, and two-port functionality. However, GC-eDRAM requires …
low leakage power, small size, and two-port functionality. However, GC-eDRAM requires …