Single-chip hardware implementation of Advanced Encryption Standard (AES) offers a low-
power and low-area design that is suitable for portable devices. It is widely applicable for …

In this paper, a unified Field Programmable Gate Array (FPGA) based Advanced Encryption
Standard (AES) encryptor/decryptor design is presented by proposing a symmetric ST-Box …

Tweakable enciphering schemes are length-preserving block cipher modes of operation that
provide a strong pseudorandom permutation. It has been suggested that these schemes can …

This paper presents a resource-shared 8-bit (RS8) architecture for the AES algorithm, which
aims at compacting the hardware architecture and allows hardware resources to be shared …

Reprogrammable devices such as Field Programmable Gate Arrays (FPGA's) are highly
attractive options for hardware implementations of encryption algorithms. Several papers …

A new class of polynomials was introduced by Bernstein (Bernstein 2007) which were later
named by Sarkar as BernsteinRabin-Winograd (BRW) polynomials (Sarkar 2009). For the …

The most critical factors responsible for bottleneck in the design and implementation of high-
speed AES (Advanced Encryption Standard) architectures for any resource constrained …

This paper proposes an efficient solution to combine Rijndael encryption and decryption in
one FPGA design, with a strong focus on low area constraints and high throughput. This …

Both area and throughput are significant for hardware implementations of the Advanced
Encryption Standard (AES). Previous works mostly focused on area without providing full …

Block ciphers are one of the most important primitives in cryptology. They are based on well-
understood mathematical and cryptographic principles. Due to their inherent efficiency …