Synchronised 4-phase resonant power clock supply for energy efficient adiabatic logic

N Jeanniot, G Pillonnet, P Nouet… - 2017 IEEE …, 2017 - ieeexplore.ieee.org
Adiabatic logic is an alternative architecture design style to reduce the power consumption
of digital cores by using AC power supply instead of DC ones. The energy saving of the …

Implementation of optimized vedic multiplier using CMOS technology

E Masurkar, P Dakhole - 2016 International Conference on …, 2016 - ieeexplore.ieee.org
This paper presents design of optimized high speed and low power Vedic multiplier based
on Vedic sutra Urdhva Tiryagbhyam. Adiabatic logic is used to reduce the power …

Design of subthreshold adiabatic logic based combinational and sequential circuits

P Kalyani, PS Kumar, PC Sekhar - … International Conference on …, 2017 - ieeexplore.ieee.org
Power dissipation in VLSI circuits has become increasingly important for modern portable
devices. Adiabatic is a novel energy conserving logic for ultra low power circuits. Adiabatic …

Power efficient odd parity generator & checker circuits

RH Vanlalchaka, S Roy - 2013 1st International Conference on …, 2013 - ieeexplore.ieee.org
This paper presents three bit odd parity generator and detector circuits based on low power
adiabatic logic technique. The paper proposes a new design approach which is being …

Theory, synthesis, and application of adiabatic and reversible logic circuits for security applications

M Morrison - 2014 IEEE Computer Society Annual Symposium …, 2014 - ieeexplore.ieee.org
Programmable reversible logic is emerging as a prospective logic design style for
implementation in modern nanotechnology and quantum computing with minimal impact on …

Parity generator & parity checker using sub-threshold adiabatic logic

P Gaurav, S Singh, SK Pandey - 2020 IEEE 7th Uttar …, 2020 - ieeexplore.ieee.org
Power dissipation becomes an essential criterion in VLSI system in the current ultra-low
power applications scenario. Sub-threshold adiabatic logic designing has shown its …

[PDF][PDF] Low Power Architecture for ASIP's: Based on Adiabatic Switching Principles

D Shinghal, AN Mishra, F Hussain… - International Journal of …, 2016 - researchgate.net
Power minimization is one of the primary concerns in today VLSI design methodologies
because of two main reasons one is the long battery operating life requirement of mobile …

Comparison of Power Efficient Inverter Circuit using adiabatic technique

MK Goel, S Bharti, P Kumar, S Dandotiya… - Journal of Physics …, 2022 - iopscience.iop.org
The power decadence in conventional CMOS (Complementary Metal oxide Semiconductor)
circuit can be diminished by utilizing adiabatic method. Working of Adiabatic logic depends …

[PDF][PDF] Adiabatic SRAM for Low Power Devices

A Saxena, K Shinghal, D Shinghal - International Journal of Recent …, 2017 - academia.edu
With modernization and requirement of computational devices having facility of having
communication anytime anywhere, there is an ever-increasing demand of battery operated …

Design of 4-bit ALU using sub-threshold adiabatic logic (SAL)

SS Pandu, AK Adibhatla - Sādhanā, 2021 - Springer
In this paper, a modified 1-bit arithmetic and logical unit (ALU) is proposed from the existing
designs and a 4-bit ALU has been developed using both CMOS and Sub-Threshold …