US10515981B2 - Multilevel semiconductor device and structure with memory - Google
Patents US10515981B2 - Multilevel semiconductor device and structure with memory …

H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state
components formed in or on a common substrate including semiconductor components …

5,793,107 A 8, 1998 Nowak 5,955,781 A 9, 1999 Joshi et al. 6,080,608 A 6, 2000 Nowak
6,110,769 A 8, 2000 Son 6,121,659 A 9, 2000 Christensen et al. 6,153,912 A 11, 2000 Holst …

A device, including: a first structure including first memory cells, the first memory cells
including first transistors; and a second structure including second memory cells, the second …

A method for processing a 3D semiconductor device, the method including: providing a
wafer including a plurality of first dies, the plurality of first dies including a first transistor layer …

(57) ABSTRACT A bonded structure can comprise a first element and a second element.
The first element has a first dielectric layer includ ing a first bonding surface and at least one …

A multilevel semiconductor device including: a first level including a first array of first memory
cells and first control line; a second level including a second array of second memory cells …

H01L23/522—Arrangements for conducting electric current within the device in operation
from one component to another, ie interconnections, eg wires, lead frames including …

A 3D memory device, the device including: a first single crystal layer including memory
peripheral circuits; a first memory layer including a first junction-less transistor; a second …

An integrated circuit assembly includes a first substrate and a second substrate, with active
layers formed on the first surfaces of each substrate, and with the second surfaces of each …