Roughly, the cycle for developing a special-purpose system can be divided into three
phases–task definition, design, and implementation. During task definition, some system …

Programmable active memories (PAM) are a novel form of universal reconfigurable
hardware coprocessor. Based on field-programmable gate array (FPGA) technology, a PAM …

A measurement of the spectral functions of non-strange τ vector current final states is
presented, using 124 358 τ pairs recorded by the ALEPH detector at LEP during the years …

A systematic folding transformation technique to fold any arbitrary signal processing
algorithm data-flow graph to a hardware data-flow architecture, for a specified folding set …

Two systolic architectures are developed for performing the product–sum computation AB+
C in the finite field GF (2 m) of 2 m elements, where A, B, and C are arbitrary elements of GF …

The problem of performing multtphcaUon of n-bit binary numbers on a chip is considered Let
A denote the ch~ p area and T the time reqmred to perform mult~ phcation. By using a model …

VLSI chip is important so that the chip area needed for interconnections will be minimal. The
possible penalty, of course, In Xout in using bit-or digit-serial transmission is slow …

A VLSI Architecture for Fast Inversion in GF(2”) Page 1 IEEE TRANSACTIONS ON
COMPUTERS. VOL 38, NO. IO. OCTOBER 1989 1383 A VLSI Architecture for Fast Inversion in …

This tutorial paper addresses some of the principles and provides examples of concurrent
architectures and designs that have been inspired by VLSI technology. The circuit density …

We introduce the concept of PAM, Programmable Active Memory and present results
obtained with our Perle-0 prototype board, featuring: A software silicon foundry for a 50K …