This paper presents delay improved VLSI architecture of S-box for Advance Encryption
Standard (AES) algorithm. The proposed architecture is implemented in FPGA. The delay …

This paper presents a 3 in 1 standalone FPGA system which can perform color image blur
detection in parallel with compression and encryption. Both blur detection and compression …

We present a new design of low-power and high-speed Discrete Cosine Transform (DCT)
for image compression to be implemented on Field Programmable Gate Arrays (FPGAs) …

The canonical signed digit (CSD) representation of constant coefficients is a unique signed
data representation containing the fewest number of nonzero bits. Consequently, for …

Broadcasting applications such as video surveillance systems are using High Definition
(HD) videos. The use of high-resolution videos increases significantly the data volume of …

A ESTRA (" T Secure data transmission plays a crucial role in today's world. While the data
in the form of images are required extensively, the need to safeguard the original images …

Existing methods when employ compression there is no consideration of security, similarly
when it describe encryption there is no consideration of size ie compression. In this paper a …

Traditional fast Discrete Cosine Transforms (DCT)/Inverse DCT (IDCT) algorithms have
focused on reducing the arithmetic complexity. In this manuscript, we implemented a new …

An efficient VLSI implementation of encryption using Advanced Encryption Standard (AES)
algorithm is introduced. The architecture deals with ROM based key expansion modules …

This paper presents an efficient VLSI architecture design of Advanced Encryption Standard
(AES) algorithm for medium throughput applications. The architecture stores the Round Key …