This paper studies the impact of L2 cache sharing on threads that simultaneously share the
cache, on a chip multi-processor (CMP) architecture. Cache sharing impacts threads …

The ever-increasing importance of main memory latency and bandwidth is pushing CMPs
towards caches with higher capacity and associativity. Associativity is typically improved by …

As processor speeds increase and memory latency becomes more critical, intelligent design
and management of secondary caches becomes increasingly important. The efficiency of …

Caches often suffer from performance cliffs: minor changes in program behavior or available
cache space cause large changes in miss rate. Cliffs hurt performance and complicate …

The cost of moving and storing data is still a fundamental concern for computer architects.
Inefficient handling of data can be attributed to conventional architectures being oblivious to …

As shared last level caches are widely used in many-core CMPs to boost system
performance, partitioning a large shared cache among multiple concurrently running …

Modern processors use high-performance cache replacement policies that outperform
traditional alternatives like least-recently used (LRU). Unfortunately, current cache models …

5,596,293 A 1/1997 Rogers et al. access operations is described in connection with a multi
5,712,791 A 1/1998 Lauterbach................. 364,489 threaded multiprocessor chip. This parity …

Efficient memory hierarchy design is critical due to the increasing gap between the speed of
the processors and the memory. One of the sources of inefficiency in current caches is the …

Bank conflicts can severely reduce the bandwidth of an interleaved multibank memory and
conflict misses increase the miss rate of a cache or a predictor. Both occurrences are …