Dynamically reconfigurable FIR filter architectures with fast reconfiguration

M Kumm, K Möller, P Zipf - 2013 8th International Workshop on …, 2013 - ieeexplore.ieee.org
This work compares two finite impulse response (FIR) filter architectures for FPGAs for which
the coefficients can be reconfigured during run-time. One is a recently proposed filter …

Multioperand redundant adders on FPGAs

J Hormigo, J Villalba, EL Zapata - IEEE Transactions on …, 2012 - ieeexplore.ieee.org
Although redundant addition is widely used to design parallel multioperand adders for ASIC
implementations, the use of redundant adders on Field Programmable Gate Arrays (FPGAs) …

Efficient FPGA implementation of digit parallel online arithmetic operators

K Shi, D Boland… - … Conference on Field …, 2014 - ieeexplore.ieee.org
Online arithmetic has been widely studied for ASIC implementation. Online components
were originally designed to perform computations in digit serial with most significant digit …

Shift-add circuits for constant multiplications

PK Meher, CH Chang, O Gustafsson… - Arithmetic circuits for …, 2017 - books.google.com
Several applications involving signal, image, and video processing, graphics and robotics,
and so on, very often require large number of multiplications, which consume a major part of …

Design methodologies for complexity reduction of FIR filters

M Faust - 2014 - dr.ntu.edu.sg
Digital signal processing is ubiquitous and many new applications have been developed for
portable wireless communication devices due to the demand for connectivity. Versatile …

[图书][B] Design of approximate overclocked datapath

K Shi - 2016 - core.ac.uk
Embedded applications can often demand stringent latency requirements. While high
degrees of parallelism within custom FPGA-based accelerators may help to some extent, it …

Architecture and Application‐Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis

S Sinha, T Srikanthan - International Journal of Reconfigurable …, 2014 - Wiley Online Library
Multiplication is a common operation in many applications and there exist various types of
multiplication operations. Current high level synthesis (HLS) flows generally treat all …

Uso eficiente de aritmética redundante en FPGAs

MA Ortiz - 2013 - helvia.uco.es
Hasta hace pocos años, la utilización de aritmética redundante en FPGAs había sido
descartada por dos razones principalmente. En primer lugar, por el buen rendimiento que …

Intelligent high level synthesis for customization on reconfigurable platforms

S Sinha - 2014 - dr.ntu.edu.sg
High level synthesis (HLS) using C/C++ has increasingly become a critical step in the
realization of complex digital systems. One of the major research focus areas in this space …

[PDF][PDF] CARLOS DIEGO MORENO MORENO

DPM JIMÉNEZ - 2013 - helvia.uco.es
Esta tesis presenta varias arquitecturas sobre la unidad MAC (multiplica–acumula) para la
optimización de la operación de convolución, que es ampliamente utilizada en el …