At the turn of this century, there was widespread concern that the performance of analog-to-
digital converters (ADCs) might have reached a saturation point and would, in fact …

Exploiting ultra-wide bandwidths is a promising approach to achieve the terabits per second
(Tbps) data rates required to unlock emerging mobile applications like mobile extended …

A 12-bit 10-GS/s interleaved (IL) pipeline analog-to-digital converter (ADC) is described in
this paper. The ADC achieves a signal to noise and distortion ratio (SNDR) of 55 dB and a …

<? Pub Dtl=""?> A time-interleaved ADC employs four pipelined time-interleaved channels
along with a new timing mismatch detection algorithm and a high-resolution variable delay …

The best beam steering directions are estimated through beam training, which is one of the
most important and challenging tasks in millimeter-wave and sub-terahertz communications …

A compact decision-error-tolerant 2b/cycle SAR ADC architecture is presented. Two DACs
with different designated functions, SIG-DAC and REF-DAC, are implemented to make the …

This paper proposes a novel all-digital background calibration of timing mismatch for a time-
interleaved analog-to-digital converter (TIADC). For two different calibration strategies, the …

This article presents a split time-interleaved (TI) successive-approximation register (SAR)
analog-to-digital converter (ADC) with digital background timing-skew mismatch calibration …

This article presents a 12-bit 1-GS/s ring-amp-based analog-to-digital converter (ADC) with
a pipelined and time-interleaved successive approximation register (TI-SAR) hybrid …

Achieving high linearity and bandwidth with good power efficiency makes the design of
ADCs in deep nanoscale CMOS processes very challenging, as the constraints of low …