BACKGROUND A solid state drive (SSD) is designed to provide reliable and high
performance storage of user data across a flash-based memory system containing a host …

A system includes a power management unit that may monitor the power consumed by a
processor including a plurality of processor core. The power management unit may throttle …

Notice: Subject to any disclaimer, the term of this Methods and apparatus for managing
latency of memory patent is extended or adjusted under 35 commands are disclosed. An …

In one form, an apparatus includes a memory controller. The memory controller includes a
command queue and an arbiter. The command queue receives and stores memory access …

Disclosed are apparatus and techniques for managing power in a memory system having a
controller and nonvolatile memory array. In one embodiment, prior to execution of each …

Embodiments of the invention are generally directed to systems, methods, and apparatuses
for improving power/performance tradeoffs associated with multi-core memory thermal …

A data processing system uses memory for storing data used by an application. Storing data
in memory and reading data from memory consumes electrical power (power). A data …

A storage controller system may include a host controller that queues host commands as
data transfer commands in a plu rality of queue channels. The storage controller system may …

Techniques and mechanisms for managing a delivery of power to a resource of an
input/output (I/O) interface. In an embodiment, a first link of a plurality of communication links …

Abstract Systems and methods are disclosed for providing memory channel interleaving with
selective power or performance optimization. One such method involves configuring a …