A method of operating a storage device, including; performing, by a non-volatile memory, an
erase operation on a block of memory in the non-volatile memory, where the non-volatile …

A variety of applications can include memory devices designed to provide stabilization of
selector devices in a memory array of the memory device. A selector stabilizer pulse can be …

A storage device may include a controller performing non data word line (NDWL)
maintenance in sub block mode (SBM). The NDWL maintenance in SBM can include …

A method for dynamically adjusting an erase voltage level to be applied in a subsequent
erase cycle, comprising: in a current erase cycle, initiating a current erase/verify loop by …

A memory management method, a memory storage device, and a memory control circuit unit
are disclosed. The method includes: sending an erase command sequence configured to …

A semiconductor memory device includes: a memory cell array including a plurality of NAND
strings, each of the plurality of NAND strings including a plurality of memory cell transistors …

A variety of applications can include memory devices designed to provide stabilization of
selector devices in a memory array of the memory device. A selector stabilizer pulse can be …

Apparatuses and techniques are described for modifying program and erase parameters in
a memory device in which memory cells can be operated in a single bit per cell (SLC) mode …

US11594295B2 - Nonvolatile memory device and method of operating the same - Google
Patents US11594295B2 - Nonvolatile memory device and method of operating the same …

In certain aspects, a memory device includes a first memory string including a first drain, a
first drain select gate (DSG) transistor, first memory cells, and a first drain dummy transistor …