Scalable and flexible communication networks increasingly conduct the packet processing
for Network Functions (NFs) in General Purpose Computing (GPC) platforms. The …

The recently released SPEC CPU2017 benchmark suite has already started receiving a lot
of attention from both industry and academic communities. However, due to the significantly …

Effective huge page management in operating systems is necessary for mitigation of
address translation overheads. However, this continues to remain a difficult area in OS …

With explosive growth in dataset sizes and increasing machine memory capacities, per-
application memory footprints are commonly reaching into hundreds of GBs. Such huge …

The unabating growth of the memory needs of emerging datacenter applications has
exacerbated the scalability bottleneck of virtual memory. However, reducing the excessive …

As memory capacity has outstripped TLB coverage, large data applications suffer from
frequent page table walks. We investigate two complementary techniques for addressing …

The unprecedented growth in the memory needs of emerging memory-intensive workloads
has made virtual memory translation a major performance bottleneck. To address this …

We propose synergistic software and hardware mechanisms that alleviate the address
translation overhead, focusing particularly on virtualized execution. On the software side, we …

Intel and AMD processors have long supported more than one large page sizes–1GB and
2MB, to reduce address translation overheads for applications with large memory footprints …

Frequent Translation Lookaside Buffer (TLB) misses incur high performance and energy
costs due to page walks required for fetching the corresponding address translations …