Novel snapback-free SOI LIGBT with shorted anode and trench barriers
L Sun, B Duan, Y Yang - IEEE Transactions on Electron …, 2021 - ieeexplore.ieee.org
A novel fast-switching silicon-on-insulator lateral insulated gate bipolar transistor (SOI
LIGBT) is proposed and investigated in this article. The proposed device introduces trench …
LIGBT) is proposed and investigated in this article. The proposed device introduces trench …
Double-gate RESURF lateral insulated gate bipolar transistor with built-in p-channel MOSFET for active conductivity modulation control throughout drift region
J Yang, M Zhang, Y Wu, M Wang… - IEEE Electron Device …, 2022 - ieeexplore.ieee.org
A double-gate RESURF lateral IGBT (DGR-LIGBT) with build-in p-channel MOSFET (p-
MOSFET) is proposed and studied by numerical TCAD simulations. In the conventional …
MOSFET) is proposed and studied by numerical TCAD simulations. In the conventional …
Integration trends in monolithic power ICs: Application and technology challenges
M Rose, HJ Bergveld - IEEE Journal of Solid-State Circuits, 2016 - ieeexplore.ieee.org
This paper highlights the general trend towards further monolithic integration in power
applications by enabling power management and interfacing solutions in advanced CMOS …
applications by enabling power management and interfacing solutions in advanced CMOS …
Ultralow turn-OFF loss SOI LIGBT with p-buried layer during inductive load switching
An ultralow turn-OFF loss (EOFF) silicon-oninsulator lateral insulated-gate bipolar transistor
with a p-buried layer (PB SOT LTGBT) is first proposed. A universal EOFF model during …
with a p-buried layer (PB SOT LTGBT) is first proposed. A universal EOFF model during …
Turn-off transient of superjunction SOI lateral IGBTs: Mechanism and optimization strategy
In this paper, five types of superjunction (SJ) configurations are investigated in the silicon-on-
insulator lateral insulated-gate bipolar transistor (SOI-LIGBT). technology computer aided …
insulator lateral insulated-gate bipolar transistor (SOI-LIGBT). technology computer aided …
Schottky-embedded isolation ring to improve latch-up immunity between HV and LV circuits in a 0.18 μm BCD technology
ZH Jiang, MD Ker - IEEE Journal of the Electron Devices …, 2022 - ieeexplore.ieee.org
As the high-voltage (HV) and low-voltage (LV) circuits are integrated together in a common
silicon substrate, the parasitic latch-up path between neighboring HV and LV circuits with …
silicon substrate, the parasitic latch-up path between neighboring HV and LV circuits with …
Latch-Up Prevention With Autodetector Circuit to Stop Latch-Up Occurrence in CMOS-Integrated Circuits
ZH Jiang, MD Ker - IEEE Transactions on Electromagnetic …, 2022 - ieeexplore.ieee.org
Due to the parasitic silicon-controlled-rectifier structure, latch-up issues have been an
inherent problem with bulk CMOS ICs. In this work, a novel design of an autodetector circuit …
inherent problem with bulk CMOS ICs. In this work, a novel design of an autodetector circuit …
[PDF][PDF] 绝缘体上硅功率半导体单芯片集成技术
张龙， 刘斯扬， 孙伟锋， 马杰， 盘成务， 何乃龙， 张森… - 电子学报, 2023 - ejournal.org.cn
利用单芯片集成技术制造的智能功率芯片具有体积小, 寄生小, 损耗低等方面的优势,
其技术难度远高于传统的多芯片, 单封装形式的智能功率模块. 本文首先介绍了单片智能功率 …
其技术难度远高于传统的多芯片, 单封装形式的智能功率模块. 本文首先介绍了单片智能功率 …
Optimization of Plateau for Deep-Oxide Trench SOI Lateral IGBT During Inductive Load Turn-OFF
Collector-emitter voltage (V CE) plateau of the 500-V deep-oxide trench (DOT) silicon-on-
insulator lateral insulated gate bipolar transistor (SOI-LIGBT) during inductive load turn-off is …
insulator lateral insulated gate bipolar transistor (SOI-LIGBT) during inductive load turn-off is …
Influence of latch-up immunity structure on ESD robustness of SOI-LIGBT used as output device
The influences of three typical latch-up immunity structures, including high concentrated P++
doping layer, N+/P+ segmented emitter and P-sink well, upon electro-static discharge (ESD) …
doping layer, N+/P+ segmented emitter and P-sink well, upon electro-static discharge (ESD) …